Renesas M16C FAMILY series Hardware Manual page 328

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1. To set the FMR01 bit to "1", write "1" to this bit immdediately after writing "0". Do not generate an
interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Set this bit while the
P8 /NMI/SD pin is held "H" when selecting the NMI function. Set by program in a space other than the
5
flash memory in EW mode 0. Set this bit to read alley mode and "0"
2. To set the FMR02 bit to "1", write "1" to this bit immediately after writing "0" while the FMR01 bit is set
to "1". Do not generate an interrupt or a DMA transfer between setting this bit to "0" and setting it to "1".
3. Set this bit in a space other than the flash memory by program. When this bit is set to "1", access to
flash memory will be denied. To set this bit to "0" after setting it to "1", wait for 10 usec. or more after
setting it to "1". To read data from flash memory after setting this bit to "0", maintain tps wait time
before accessing flash memory.
4. This bit is set to "0" by executing the clear status command.
5. This bit is enabled when the FMR01 bit is set to "1" (CPU rewrite mode). If the FMR01 bit is set to 0",
this bit can be set to "1" by writing "1" to the FMR01 bit. However, the flash memory does not enter
low-power consumption status and it is not initialized.
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1. To set the FMR11 bit to "1", write "1" to this bit immediately after writing "0" while the FMR01 bit is set to
"1". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1".Set this
bit while the P8
FMR01 bit and FMR11 bit are both set to "0".
2. To set the FMR16 bit to "1", write "1" to this bit immediately after writing "0" while the FMR01 bit is set to
"1". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1".
3. When rewriting more than 100 times, set this bit to "1" (with wait state). When the FMR17 bit is set to
"1"(with wait state), regardless of the PM17 bit setting, 1 wait state is inserted when accessing to blocks A
and B. The PM17 bit setting is enabled, regardless of the FMR17 bit setting, as to the access to other block
and the internal RAM.
Figure 18.7 FMR0 and FMR1 Registers
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Symbol
0 FMR0
Bit Symbol
RY/BY status flag
FMR00
CPU rewrite mode select bit
FMR01
Block 0, 1 rewrite enable bit
FMR02
Flash memory stop bit
FMSTP
Reserved bit
(b5-b4)
FMR06 Program status flag
FMR07 Erase status flag
Symbol
FMR1
Bit Symbol
Reserved bit
(b0)
FMR11
EW mode 1 select bit
Reserved bit
(b3-b2)
Nothing is assigned. When write, set to "0".
(b4)
When read, its contect is indeterminate.
Reserved bit
(b5)
Block 0 to 5 rewrite enable
FMR16
(2)
bit
FMR17 Block A, B access wait bit
/NMI/SD pin is held "H" when the NMI function is selected. If the FMR01 bit is set to "0", the
5
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f o 3 8 5
Address After Reset
01B7 00000001
16 2
Bit Name
0: Busy (during writing or erasing)
1: Ready
(1) 0: Disables CPU rewrite mode
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
Set write protection for user ROM area
(2)
(see Table 18.4)
0: Starts flash memory operation
(3, 5)
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
Set to "0"
0: Successfully completed
(4)
1: Completion error
0: Successfully completed
1: Completion error
(4)
Address After Reset
01B5 000XXX0X
16 2
Bit Name
When read, its content is indeterminate
(1)
0: EW mode 0
1: EW mode 1
When read, its content is indeterminate
Set to "0"
Set write protection for user ROM
space(see Table 18.4)
0: Disable
1: Enable
(3)
0: PM17 enabled
1: With wait state (1 wait)
18. Flash Memory Version
Function RW
RO
RW
RW
RW
RW
RO
RO
Function
RW
RO
RW
RO
RW
RW
RW