Renesas M16C FAMILY series Hardware Manual page 189
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- User manual (501 pages)
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M
1
6
C
2 /
8
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o r
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p
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M
1
6
C
UARTi Transmit Buffer Register (i=0 to 2)
(b15)
b7
NOTES:
1. Use MOV instruction to write to this register.
UARTi Receive Buffer Register (i=0 to 2)
(b15)
b7
NOTES:
1. When the SMD2 to SMD0 bits in the UiMR register are set to "000
disabled), all of the SUM, PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error) when all of the PER, FER and OER
bits are set to "0" (no error). Also, the PER and FER bits are set to "0" by reading the lower byte of the UiRB register.
2. The ABT bit is set to "0" by setting to "0" by program. (Writing "1" has no effect.)
Nothing is assigned at the bit 11 in the U0RB and U1RB registers. When write, set to "0". When read, its content is "0".
UARTi Baud Rate Generation Register (i=0 to 2)
b7
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
The transfer clock is shown below when the setting value in the UiBRG register is set as n.
(1) When the CKDIR bit in the UiMR register to "0" (internal clock)
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O (UART) mode
(2) When the CKDIR bit in the UiMR register to "1" (external clock)
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O (UART) mode
3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 registers.
Figure 14.4 U0TB to U2TB, U0RB to U2RB, U0BRG to U2BRG Registers
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2
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0
J
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3
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2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
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M
1
6
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2 /
8
) B
(1)
Symbol
(b8)
U0TB
b0
b7
b0
U1TB
U2TB
Transmit data
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
(b8)
Symbol
b0
b7
b0
U0RB
U1RB
U2RB
Bit
Symbol
(b7-b0)
(b8)
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
(b10-b9)
Arbitration lost detecting
ABT
flag
Overrun error flag
OER
FER
Framing error flag
PER
Parity error flag
SUM
Error sum flag
Symbol
b0
U0BRG
U1BRG
U2BRG
Assuming that set value = n, UiBRG divides the count source
by n + 1
page 169
f o
3
8
5
Address
After Reset
03A3
-03A2
Indeterminate
16
16
03AB
-03AA
Indeterminate
16
16
037B
-037A
Indeterminate
16
16
Function
Address
After Reset
03A7
-03A6
Indeterminate
16
16
03AF
-03AE
Indeterminate
16
16
037F
-037E
Indeterminate
16
16
Bit Name
Receive data (D
Receive data (D
0 : Not detected
1 : Detected
(2)
(1)
0 : No overrun error
1 : Overrun error found
(1)
0 : No framing error
1 : Framing error found
(1)
0 : No parity error
1 : Parity error found
(1)
0 : No error
1 : Error found
" (serial I/O disabled) or the RE bit in the UiC1 register is set to "0" (reception
2
(1, 2, 3)
Address
After Reset
03A1
Indeterminate
16
03A9
Indeterminate
16
0379
Indeterminate
16
Function
: fj/(2(n+1))
: fj/(16(n+1))
: f
EXT
: f
/(16(n+1))
EXT
fj : f1SIO, f2SIO, f8SIO, f32SIO
f
: Input from CLKi pin
EXT
Function
to D
)
7
0
)
8
Setting Range
00
to FF
16
16
14. Serial I/O
RW
WO
RW
RO
RO
RW
RO
RO
RO
RO
RW
WO
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