Renesas M16C FAMILY series Hardware Manual page 63

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
CPU
DMAC
CPU clock
Clock
generation
circuit
Figure 6.3 Bus Block Diagram
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
Table 6.1 Accessible Area and Bus Cycle
SFR PM20 bit = 0 (2 waits)
PM20 bit = 1 (1 wait)
ROM/RAM PM17 bit = 0 (no wait)
PM17 bit = 1 (1 wait)
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
CPU address bus
BIU
CPU data bus
Peripheral function
Accessible Area
3 CPU clock cycles
2 CPU clock cycles
1 CPU clock cycle
2 CPU clock cycles
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f o 3 8 5
ROM
Memory address bus
Memory data bus
Timer
WDT
Serial I/O
ADC
I/O
Bus Cycle
6. Processor Mode
RAM
.
.
.
.