Renesas M16C FAMILY series Hardware Manual page 276

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
2
I C0 Control Register 1
b7 b6 b5 b4
NOTES:
1. The PED and PEC bits are enabled when the ES0 bit in the S1D0 register is set to "1"(I
2. When the PCLK0 bit in the PCLKR register is set to "0", f
to "1", f =f
IIC
Figure 16.6 S3D0 Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b3 b2 b1 b0
Symbol
S3D0
Bit Symbol
SIM The Interrupt Enable Bit for
STOP Condition Detection
WIT The Interrupt Enable Bit for
Data Receive Completion
S
PED
Bit
S
PEC
Bit
The Logic Value Monitor
SDAM
Bit of S
The Logic Value Monitor
SCLM
Bit of S
2
ICK0
I C bus System Clock
Selection Bits,
if ICK4 to ICK2 bits in the
ICK1
S4D0 register is "000
.
1
page 256
f o 3 8 5
Address
02E6
16
Bit Name
0: Disable the I
1: Enable the I
0: Disable the I
1: Enable the I
When setting NACK
(ACK bit = 0), write "0"
/Port Function Switch 0: S
DAi
(1)
1: Port output pin (enable ES0 = 1)
/Port Function Switch 0: S
CLi
(1)
1: Port output pin (enable ES0 = 1)
0: S
Output 1: S
DA
0: S
Output
1: S
CL
b7 b6
0 0 :
0 1 :
1 0 :
"
2
1 1 : Reserved
=f . When the PCLK0 bit in the PCLKR register is set
IIC 2
2
16. MULTI-MASTER I
After Reset
00110000
2
Function
2
C bus interface
interrupt of STOP condition
detection
2
C bus interface
interrupt of STOP condition
detection
2
C bus interface
interrupt upon completion
of receiving data
2
C bus interface
interrupt upon completion of
receiving data
I/O pin (enable ES0 = 1)
DA
I/O pin (enable ES0 = 1)
CL
output logic value = 0
DA
output logic value = 1
DA
output logic value = 0
CL
output logic value = 1
CL
=1/2 f
V IIC
IIC
V =1/4f
IIC IIC
=1/8 f
V
IIC
IIC
(2)
2
C bus interface enabled).
C bus INTERFACE
RW
RW
RW
RW
RW
RO
RO
RW
RW