Renesas M16C FAMILY series Hardware Manual page 255

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
A/D Trigger Control Register
b7 b6 b5
NOTES:
1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 15.18 ADTRGCON Register in Simultaneous Sample Sweep Mode
Table 15.9 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
TRG1 HPTRG0
TRG
- -
0
-
1
1
1 0
0
1 1 0
NOTES:
1. A count can be started for Timer B2, Timer B2 interrupt generation frequency
setting counter underflow or the INT5 pin falling edge as count start
conditions of Timer B0.
2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter
using the TB2SEL bit in the TB2SC register.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
(1)
b4 b3 b2 b1 b0
Symbol
0
0 1
ADTRGCON
Bit Symbol
SSE
DTE
HPTRG0
HPTRG1
(b7-b4)
TRIGGER
Software trigger
(1)
Timer B0 underflow
AD
TRG
Timer B2 or Timer B2 interrupt generation frequency setting
(2)
counter underflow
page 235
f o 3 8 5
Address After Reset
03D2 00
16 16
Bit Name
1 : Simultaneous sample sweep mode
A/D Operation Mode
or delayed trigger mode 0, 1
Select Bit 2
0 : Any mode other than delayed trigger
A/D Operation Mode
Select Bit 3
Refer to Table 15.9
AN0 Trigger Select Bit
Set to "0" in simultaneous sample
AN1 Trigger Select Bit
sweep mode
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Function
mode 0,1
15. A/D Converter
RW
RW
RW
RW
RW