Renesas M16C FAMILY series Hardware Manual page 281

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Table 16.3 Setting values of S20 register and SCL frequency
Setting value of CCR4 to CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
1 1 1
1 1 1
1 1 1
NOTES:
1. The duty of the SCL clock output is 50 %. The duty becomes 35 to 45 % only when high-speed
clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). "H" duration of the
clock fluctuates from –4 to +2 I
2
–2 to +2 I C system clock cycles in high-speed clock mode. In the case of negative fluctuation, the
frequency does not increase because the "L" is extended instead of "H" reduction. These are the
values when the SCL clock synchronization by the synchronous function is not performed. The
CCR value is the decimal notation value of the CCR4 to CCR0 bits.
2. Each value of the SCL frequency exceeds the limit at V
setting values, use V
3. The data formula of SCL frequency is described below:
V /(8 x CCR value) Standard clock mode
IIC
V /(4 x CCR value) High-speed clock mode (CCR value
IIC
V /(2 x CCR value) High-speed clock mode (CCR value = 5)
IIC
Do not set 0 to 2 as the CCR value regardless of the VIIC frequency. Set 100 kHz (max.) in
standard clock mode and 400 kHz (max.) in high-speed clock mode to the SCL frequency by
setting the CCR4 to CCR0 bits.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
SCL frequency (at V
Standard clock mode
0 0 Setting disabled
0 1 Setting disabled
1 0 Setting disabled
1 1
0 0
0 1
1 0
500 / CCR value
0 1
1 0
1 1
2
C system clock cycles in standard clock mode, and fluctuates from
= 4 MHz or less. Refer to Figure 16.6.
IIC
page 261
f o 3 8 5
16. MULTI-MASTER I
=4MHz, unit : kHz)
IIC
- (2)
- (2)
100
83.3
(3)
17.2
16.6
16.1
= 4 MHz or more. When using these
IIC
≠
5)
2
C bus INTERFACE
(1)
High-speed clock mode
Setting disabled
Setting disabled
Setting disabled
333
250
400 (3)
166
1000 / CCR value (3)
34.5
33.3
32.3