Renesas M16C FAMILY series Hardware Manual page 101

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Priority level of each interrupt
IC/OC interrupt 1, I
IC/OC base timer, S
IC/OC interrupt 0
UART1 reception
UART0 reception
UART2 reception, ACK2
A/D conversion
UART 2 bus collision
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
Key input interrupt
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Low voltage detection
Figure 9.10 Interrupts Priority Select Circuit
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Level 0 (initial value)
INT1
Timer B2
Timer B0
Timer A3
Timer A1
2 C bus interface
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
/S
CL DA
DMA1
SI/O4, INT5
Timer A0
DMA0
SI/O3, INT4
IPL
I flag
DBC
NMI
page 81
f o 3 8 5
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock
generation circuit (Figure 7.1)
9. Interrupts
Interrupt
request
accepted