Renesas M16C FAMILY series Hardware Manual page 13

16-bit single-chip microcomputer
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16.6.6 Address Receive in STOP/WAIT Mode ............................................................... 269
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C0 Control Register 2 (S4D0 Register) ................................................................... 270
16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) .......................................... 271
16.7.2 Bit1: Time-Out Detection Flag (TOF ).................................................................. 271
16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) .......................................... 271
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16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP) .......................................... 272
16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS) ...................................................... 272
16.9 START Condition Generation Method ....................................................................... 273
16.10 START Condition Duplicate Protect Function ........................................................... 274
16.11 STOP Condition Generation Method ........................................................................ 274
16.12 START/STOP Condition Detect Operation ............................................................... 276
16.13 Address Data Communication ................................................................................. 277
16.13.1 Example of Master Transmit ............................................................................. 277
16.13.2 Example of Slave Receive ................................................................................ 278
16.14 Precautions ............................................................................................................... 279
17. Programmable I/O Ports ............................................................................282
17.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ......................................................... 282
17.3 Pull-up Control Register 0 to 2 (PUR0 to PUR2 Registers) ........................................ 282
17.5 Pin Assignment Control Register (PACR) ................................................................... 283
17.6 Digital Debounce Function ......................................................................................... 283
18. Flash Memory Version ...............................................................................296
18.1 Flash Memory Performance ....................................................................................... 296
18.1.1 Boot Mode ........................................................................................................... 297
18.2 Memory Map ............................................................................................................... 298
18.3 Functions To Prevent Flash Memory from Rewriting .................................................. 302
18.3.1 ROM Code Protect Function ................................................................................ 302
18.3.2 ID Code Check Function ...................................................................................... 302
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A-6

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