Ppc440X5 Organization; Superscalar Instruction Unit; Figure 1-1. Ppc440 Core Block Diagram - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

1.3 PPC440x5 Organization

The PPC440x5 core includes a seven-stage pipelined PowerPC core, which consists of a three stage, dual-
issue instruction fetch and decode unit with attached branch unit, together with three independent, 4-stage
pipelines for complex integer, simple integer, and load/store operations, respectively. The PPC440x5 core
also includes a memory management unit (MMU); separate instruction and data cache units; JTAG, debug,
and trace logic; and timer facilities.
Figure 1-1 illustrates the logical organization of the PPC440x5 core:

Figure 1-1. PPC440 Core Block Diagram

1.3.1 Superscalar Instruction Unit

The instruction unit of the PPC440x5 core fetches, decodes, and issues two instructions per cycle to any
combination of the three execution pipelines and/or the APU interface (see "Execution Pipelines" below, and
Auxiliary Processor Unit (APU) Port on page 36). The instruction unit includes a branch unit which provides
dynamic branch prediction using a branch history table (BHT), as well as a branch target address cache
(BTAC). These mechanisms greatly improve the branch prediction accuracy and reduce the latency of taken
branches, such that the target of a branch can usually be executed immediately after the branch itself, with no
penalty.
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128-bit
Instruction Cache
PLB
Size Configurable)
(
I-Cache Controller
Instruction Branch
Unit Unit
Target
Addr
Issue Issue
Cache
0
1
Complex Simple
GPR
Integer Integer
File
Pipe
MAC
Data Cache
(Size Configurable)
MMU
Load/Store Queues
64-entry
D-Cache Controller
4KB
BHT
Load
GPR
Store
File
Pipe Pipe
Preliminary
128-bit
PLB
overview.fm.
September 12, 2002