Timers; Debug Facilities; Debug Modes - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core Preliminary

1.3.5 Timers

The PPC440x5 contains a Time Base and three timers: a Decrementer (DEC), a Fixed Interval Timer (FIT),
and a Watchdog Timer. The Time Base is a 64-bit counter which gets incremented at a frequency either
equal to the processor core clock rate or as controlled by a separate asynchronous timer clock input to the
core. No interrupt is generated as a result of the Time Base wrapping back to zero.
The DEC is a 32-bit register that is decremented at the same rate at which the Time Base is incremented.
The user loads the DEC register with a value to create the desired interval. When the register is decremented
to zero, a number of actions occur: the DEC stops decrementing, a status bit is set in the Timer Status
Register (TSR), and a Decrementer exception is reported to the interrupt mechanism of the PPC440x5 core.
Optionally, the DEC can be programmed to reload automatically the value contained in the Decrementer
Auto-Reload register (DECAR), after which the DEC resumes decrementing. The Timer Control Register
(TCR) contains the interrupt enable for the Decrementer interrupt.
The FIT generates periodic interrupts based on the transition of a selected bit from the Time Base. Users can
select one of four intervals for the FIT period by setting a control field in the TCR to select the appropriate bit
from the Time Base. When the selected Time Base bit transitions from 0 to 1, a status bit is set in the TSR
and a Fixed Interval Timer exception is reported to the interrupt mechanism of the PPC440x5 core. The FIT
interrupt enable is contained in the TCR.
Similar to the FIT, the Watchdog Timer also generates a periodic interrupt based on the transition of a
selected bit from the Time Base. Users can select one of four intervals for the watchdog period, again by
setting a control field in the TCR to select the appropriate bit from the Time Base. Upon the first transition
from 0 to 1 of the selected Time Base bit, a status bit is set in the TSR and a Watchdog Timer exception is
reported to the interrupt mechanism of the PPC440x5 core. The Watchdog Timer can also be configured to
initiate a hardware reset if a second transition of the selected Time Base bit occurs prior to the first Watchdog
exception being serviced. This capability provides an extra measure of recoverability from potential system
lock-ups.
The timer functions of the PPC440x5 core are more fully described in Chapter 7, "Timer Facilities."

1.3.6 Debug Facilities

The PPC440x5 debug facilities include debug modes for the various types of debugging used during hard-
ware and software development. Also included are debug events that allow developers to control the debug
process. Debug modes and debug events are controlled using debug registers in the chip. The debug regis-
ters are accessed either through software running on the processor, or through the JTAG port.
The debug modes, events, controls, and interfaces provide a powerful combination of debug facilities for
hardware development tools, such as the RISCWatch™ debugger from IBM.
A brief overview of the debug modes and development tool support are provided below. Chapter 8, "Debug
Facilities," provides detailed information about each debug mode and other debug resources.

1.3.6.1 Debug Modes

The PPC440x5 core supports four debug modes: internal, external, real-time-trace, and debug wait. Each
mode supports a different type of debug tool used in embedded systems development. Internal debug mode
supports software-based ROM monitors, and external debug mode supports a hardware emulator type of
debug. Real-time-trace mode uses the debug facilities to indicate events within a trace of processor execu-
overview.fm.
Page 34 of 589 September 12, 2002