Integer Exception Register (Xer); Figure 2-7. Integer Exception Register (Xer) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

2.6.2 Integer Exception Register (XER)

The XER records overflow and carry indications from integer arithmetic and shift instructions. It also provides
a byte count for string indexed integer storage access instructions (lswx and stswx). Note that the term
exception in the name of this register does not refer to exceptions as they relate to interrupts, but rather to the
arithmetic exceptions of carry and overflow.
Figure 2-7 illustrates the fields of the XER, while Tables 2-25 and 2-26 list the instructions which update
XER[SO,OV] and the XER[CA] fields, respectively. The sections which follow the figure and tables describe
the fields of the XER in more detail.
Access to the XER is non-privileged.
CA
SO
0 1 2 3
OV

Figure 2-7. Integer Exception Register (XER)

Summary Overflow
0 No overflow has occurred.
0 SO
1 Overflow has occurred.
Overflow
0 No overflow has occurred.
1 OV
1 Overflow has occurred.
Carry
0 Carry has not occurred.
2 CA
1 Carry has occurred.
3:24 Reserved
25:31 TBC Transfer Byte Count
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24 25
set mtspr
Can be by or by integer or auxiliary
processor instructions with the [o] option; can be
reset mtspr mcrxr
by or by
set mtspr
Can be by or by integer or allocated
instructions with the [o] option; can be
mtspr mcrxr
, by , or by integer or allocated
instructions with the [o] option.
set mtspr
Can be by or by certain integer arith-
metic and shift instructions; can be
mtspr mcrxr
, by , or by certain integer arithmetic
and shift instructions.
lswx
Used as a byte count by
dlmzb mtspr.
by [.] and by
Preliminary
TBC
31
.
reset
by
reset
by
stswx
and ; written
prgmodel.fm.
September 12, 2002