Interrupts And Exceptions; Overview; Interrupt Classes; Asynchronous Interrupts - IBM PPC440X5 CPU Core User Manual

Preliminary

6. Interrupts and Exceptions

This chapter begins by defining the terminology and classification of interrupts and exceptions in "Overview"
and "Interrupt Classes".
Interrupt Processing on page 162 explains in general how interrupts are processed, including the require-
ments for partial execution of instructions.
Several registers support interrupt handling and control. Interrupt Processing Registers on page 165
describes these registers.
Table 6-2 Interrupt and Exception Types on page 175 lists the interrupts and exceptions handled by the
PPC440x5, in the order of Interrupt Vector Offset Register (IVOR) usage. Detailed descriptions of each inter-
rupt type follow, in the same order.
Finally, Interrupt Ordering and Masking on page 199 and Exception Priorities on page 202 define the priority
order for the processing of simultaneous interrupts and exceptions.

6.1 Overview

An interrupt is the action in which the processor saves its old context (Machine State Register (MSR) and
next instruction address) and begins execution at a pre-determined interrupt-handler address, with a modified
MSR. Exceptions are the events that may cause the processor to take an interrupt, if the corresponding inter-
rupt type is enabled.
Exceptions may be generated by the execution of instructions, or by signals from devices external to the
PPC440x5 core, the internal timer facilities, debug events, or error conditions.

6.2 Interrupt Classes

All interrupts, except for Machine Check, can be categorized according to two independent characteristics of
the interrupt:
• Asynchronous or synchronous
• Critical or non-critical

6.2.1 Asynchronous Interrupts

Asynchronous interrupts are caused by events that are independent of instruction execution. For asynchro-
nous interrupts, the address reported to the interrupt handling routine is the address of the instruction that
would have executed next, had the asynchronous interrupt not occurred.

6.2.2 Synchronous Interrupts

Synchronous interrupts are those that are caused directly by the execution (or attempted execution) of
instructions, and are further divided into two classes, precise and imprecise.
intrupts.fm.
September 12, 2002
User's Manual
PPC440x5 CPU Core
Page 159 of 589