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Spare Pos
Boards
/0.., Dl
21
17
13
9
000000
Spare Pos.
Board CZ
19
15
11
8 6 4 2
000000000
11a
I
14
I
10
20
16
12
COMPONENT SI DE
B02
4.8 OPERATIONAL OUT--SINGLESHO'I'
The system/360 standard interface contains
a singleshot (A-E1G7) with an adjustable
potentiometer on it to adjust the
operational-out signal.
4. 8.1 ADJUSTMENT
scope A-E1G7D12 and adjust the lower
potentiometer on A-E1G7, while pressing the
system reset key, to obtain a negative
pulse of 8. 0 us +1/-0 us.
4.8.2 CHECKOUT PROCEDURE
-----------------002
Operational-out singleshot is checked in
routine
3
(YM03) in the channel
microdiagnostic *600.
See instructions in
routine YM03 for adjustments.
Figure 4-6.
SCR Card Cable-Connecting
Terminals
4 .6.1 REPLACEMENT
Connect the signal to the input pin of the
spare circuit to be used.
Replace the wire
to the indicator lamp with the spare cable
1 ead to be used.
4. 7 srsT.EM RESET, IPL11 OR CSL--SINGLESHOT
The CPU contains a singleshot that is
activated when the system reset. IPL, or
ICPL switches are pressed.
Its purpose is
to prevent switch l:ounce noise from
stopping the CPU clock.
4. 7.1 ADJUSTMENI'
1.
Turn the process switch
to
single cycle
and press the system reset key.
2.
Adjust the s ingleshot (logic PF 251> to
30
ms
±5 ms. using the upper
potentiometer (Figure 4-7).
SS Input
A-A2H7B02
SS Input
A-A2H7D04
-1
±sms~
Figure 4-7.
System Reset, IPL or CSL
(Singleshot)
4-8
( 7/69)
4.9 2540 ATTACHMENT
The optional 2540 attachment consists of
two SLT boards located in the A-gate. E2,
and E3.
Three leading-edge time delay
cards are located at A-E3DS, A-E3ES, and
A-:-E3E4.
4.9.1 SPECIFICATIONS
The 2540 attachment clock is driven from a
1 .• 667 megahertz oscillator located in the
A-E3 board.
This provides a 4.8 us clock
cycle for communication with the 2540 and
the attachment in the CPU.
The timing for the three leading-edge
time delay cards are as follows.
Location
A-E3D5
A-E3E5
A-E3E4
Timing
150 us,
2.2 ms,
5 .5 ms,,
4.9.2 ADJUSTMENTS
+20/-0 us
+50/-50 us
+0/-100 us
The adjustments for the three leading-edge
time delay cards are made using the
following routines in the nonresident
microdiagnostics.
card Location
A-E3DS
A-E3E5
A-E3E4
Microdiaqnostic
VM07 (Reader-Punch)
VM08 (Reader-Punch)
VM20 (Reader-Punch)
4.
10
PR-KB (10 52-7) --SINGIESHOTS
Logic
RT015
RT021
RT041
The PR-KB attachment circuitry is located
on the A-gate, A2 board.
The circuitry
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