Figure 5-2. Effective-To-Real Address Translation Flow - IBM PPC440X5 CPU Core User Manual

Preliminary
The Real Page Number (RPN) and Extended Real Page Number (ERPN) fields of the matching TLB entry
provide the page number portion of the real address. Let n=32–log
specified by the SIZE field of the matching TLB entry. Bits n:31 of the effective address (the "page offset") are
appended to bits 0:n–1 of the RPN field, and bits 0:3 of the ERPN field are prepended to this value to produce
the 36-bit real address (that is, RA = ERPN
Figure 5-2 illustrates the address translation process, while Table 5-3 defines the relationship between the
different page sizes and the real address formation.
MSR[DS] for data storage accesses
MSR[IS] for instruction fetch
PID
0

Figure 5-2. Effective-to-Real Address Translation Flow

mmu.fm.
September 12, 2002
|| RPN
0:3 0:n–1
7 0
41-bit Virtual Address
64-entry TLB
ERPN
0:3
Extended
RPN
0 3 0
(page size in bytes) where page size is
2
|| EA ).
n:31
32-bit Effective Address
Effective Page Number (EPN)
RPN
0:n-1
Real Page Number (RPN)
36-bit Real Address
User's Manual
PPC440x5 CPU Core
Offset
n–1 n 31
Offset
n–1 n 31
page size
NOTE: n = 32–log (
2
Page 141 of 589
)