Sony GY-8240UWD Maintenance Manual page 438

SV-205 board:
The SV-205 board controls operations of motors and
plungers according to the command of SYS CPU and
information from the various sensors, and it transmits
necessary information to the SYS CPU.
Main functions are as follows.
. Control of the drum motor phase
. Control of the speed by the T reel motor and control of
the T-side tension
. Control of the S-side tension by the S reel motor
. Control of the capstan motor speed
. CTL tracking, auto tracking (ATF, SAT)
. Controls of the cassette compartment, threading, reel
shift mechanism
. Generation of the record CTL
. Hours meter
. Plunger control of the reel brake, pinch roller and
cleaning roller
. Automatic adjustment, self-diagnosis
This board comprises the two CPUs (IC814 SV-1, IC902
SV-2) combined by the high-speed serial transmission, the
IC (IC805) for PLL control, the motor driver and the
external flash memory.
The SV-1 CPU mainly processes the capstan motor
control, auto tracking, SYS interface and auto adjustment.
The transmission between the SV1 CPU and the SYS CPU
(IC118) on the FM-75 board is performed through the
common memory on the FM-75 board.
The SV-2 CPU mainly plays a role in processing the
various sensors, controlling the reel motor, measuring the
drum motor rotary phase, controlling the cassette compart-
ment, threading, reel shift mechanism, plunger, and
generating the record CTL.
Transmission between the SV-1 CPU and SV-2 CPU is
performed by the high-speed transmission.
The IC for PLL control (IC805) controls the speed of the
drum motor and capstan motor.
On the external flash memory, the adjustment data and
error log are stored.
The firmware is stored on the flash memory incorporated
in the SV-1 and SV-2 CPUs.
CT-205 board:
The CT-205 board interfaces between the CPU (IC814,
IC902) on the SV-205 board/ the SYS CPU (IC118) on the
FM-75 board and the longitudinal head and transmits the
longitudinal track information.
Main functions are as follows.
. CTL record/playback amplification
. CTL CONFI amplification
. Time code record/playback amplification
. Time code CONFI amplification
. Full erase oscillation circuit
. Channel (CTL, TC) erase oscillation circuit
IF-780 board:
The IF-780 board is a 32-bit multi bus master circuit. The
bus master comprises the CPU (IC11) and NIC (IC13), and
as the bus arbiter, the one incorporated in the CPU is used.
The peripheral devices connected to the buses are as
follows.
(1) FLASH ROM (IC15)
This stores the CPU starting program and the firmware.
512kB.
(2) SDRAM (IC23, 24)
This is the main memory of the CPU and contains a 16MB
capacity by 64M bitx2.
(3) SRAM (IC17, 19, 43,44)
This is backed up by the capacitor and used for the system
log storage and for the common memory between the CPU
and NIC. It contains the 2MB capacity by 4M bitx4 and
uses each 1MB for the log and the common memory.
(4) NVRAM (IC12)
This is a nonvolatile memory for storing the system
information. 8kB.
(5) IOC (IC1)
This controls five UART, the LED for debug, and the
parallel ports.
Each UART incorporates a 32-byte FIFO, and supports the
simultaneous communications of the maximum 38.4 kbps
for each chancel by polling in every 5mS.
8-2
(6) MBC (IC9)
The IF bus is connected to a DPRAM on other CPU board
through the MB-887. The MBC opens/closes the MB-887
boundary buffer and gives/receives the control signal
between the DPRAM and the CPU. As the MBC also plays
a role in controlling the interruption, it masks the individu-
al interrupt signal from each device and encodes the signal
so as to be distinguished by the CPU.
(7) ETHC (IC10)
This is a glue-logic in order to match the CPU with the
NIC control signal.
(8) NIC (IC13)
This is the network interface controller (NIC) correspond-
ing to 10Base/T. It normally receives the register access
from the CPU as a slave. According as the setting, when
the data transmission between the network and the CPU is
required, it controls the internal FIFO and turns to be the
bus master, and it controls the SRAM of the common
memory between the network and the CPU.
DSP-90 board:
The DSP-90 board controls the LCD, LED and switches on
the front panel. This board can operate by receiving the
control command or the status sense command from the IF-
780 board.
Main functions are as follows.
. Control of LCD display
. Acceptance of inputting the command by the switches on
the front panel
. Control of front panel LED display
. Control of the buzzer sound
. Sense of the cassette sensor status
. Control of memory label I/F
SCS-28 board (GY-8240UWD):
The SCS-28 board interfaces between the SCSI Fast-20
Differential Wide and the bus.
When booting, the firmware is transmitted from the FMT
CPU to the SCSI/PCI IF (IC11) through the bus and this
IC11 controls the SCSI bus. The IC11 transmits the SCSI
command sent from the host to the FMT CPU and transfers
the data to the FM-75 board through the bus.
8-2
FC-82 board (GY-8240FC):
The FC-82 board interfaces between the Fibre Channel and
the bus.
When booting, the firmware is transmitted from the FMT
CPU to the Fibre Channel Intelligent Chip (IC4) through
the bus and this IC4 controls the Fibre Channel I/F. The
IC4 transmits the command sent from the host to the FMT
CPU and transfers the data to the FM-75 board through the
bus.
CCM-33 and SE-606 boards:
The CCM-33 and SE-606 boards constitute the Tele-File
system.
Tile-File system is the communication system using non-
contact memory. By using this system, the data such as file
information and others of the cassette tape can read and
write from/to the Tile-File Memory Label pasted on the
backside of the cassette tape.
The CCM-33 board controls the Tile-File system.
The SE-606 board is the antenna board, and this board
reads and writes the communication data between CCM-33
board and Tele-File Memory Label.
SE-533 board:
The SE-533 board detects that the cassette tape exists or
not in the cassette compartment at the cassette compart-
ment is up state.
This detection is performed by detecting the front lid of the
cassette compartment is opened state or not.
GY-8240UWD
GY-8240FC