Block Diagram And Frame Wiring; Circuits Descriptions - Sony GY-8240UWD Maintenance Manual

Section 8

Block Diagram and Frame Wiring

8-1. Circuits Descriptions

. Refer to the block diagram in section 8-2 at the same
time.
FM-75 board:
On the FM-75 board, the CPU (IC101) for controlling the
data transmission and the CPU (IC118) for controlling the
system are mounted. As flash ROMs are used for these
CPUs, their firmware can be updated without changing
ROMs.
The main functions of the CPU for controlling the data
(hereunder it is called FMT CPU) are as follows.
. Control of the SCSI controller (SCS-28 board)
. Control of the data compression
. Control of the buffer memory
. Control of the file and table
. Transmission between the IF CPU and SYS CPU
through the DP-RAM
. Self-diagnosis
(1) SCSI CMD system:
The command controls the SCSI controller (IC11) on the
SCS-28 board by being transferred on the bus from the
FMT CPU through the bus master IC (IC1) and its control
IC (IC4).
(2) SCSI DATA system:
The data is transferred on the bus through the bus master
IC (IC15) and its control IC (IC19), and temporarily stored
in the DATA STORE SRAM (IC20 to IC24). After that,
via the compression chip (IC26) it is sent to the BANK
CONTROL IC (IC30). The BANK CONTROL IC controls
the buffer memory comprising the ten 64M SDRAM and
transmits/ receives the data to/ from the DPR-160 board.
The data is added the sub code by the FMT CPU in every
ID and stored in the buffer memory. The I/O bus width of
the buffer memory is 80 bit (DATA 64 bit parity 16 bit).
Logically this buffer memory is divided into eight banks.
On the other hand, the CPU for controlling the system
(IC118 SYS CPU) performs the following controls.
. Transmission between this CPU and the IF CPU, FMT
CPU, servo CPU via the DP-RAM
. Control of writing/reading the time code.
. Timing control of writing/reading the tape
. Retry control of writing/reading the data
. Self-diagnosis
GY-8240UWD
GY-8240FC
DPR-160 board:
(1) ECC encoder (IC12-20)
The ECC encoder mainly adds the error correction code to
the data, and after adding, performs the data shuffling.
The data in the buffer memory on the FM-75 board is sent
to the ECC encoder (IC12-20 C1/C2 ENCODER) block,
where the double error correction code Reed-Solomon is
added.
The ECC encoder block performs the followings as well.
. Addition of the C2 error correction code
The 27-byte C2 error correction (parity) code is added to
the 77-byte data.
. After adding the C2 error correction code, the data
shuffling called as interleave between the tracks is
performed. The method of the interleave between the
tracks is deeply related to the correction ability of the
correction code, and when reading out the data from a
tape, even if the one track of data error is detected, C2
correction circuit can return the data.
. Addition of the SYNC BLOCK-ID
. Addition of the C1 error correction code
The 12-byte error correction code is added to the 192-
byte data.
. Randomization
All data is dispersed as the pseudo random data.
(2) Word interleave
The data is shuffled as a unit consisting of four C1 error
correction codes. Ever if a successive error of a maximum
of 20 bytes arises, by this operation, the error is divided
into four C1 error correction codes (each 5 bytes), so that
the data can be returned by the C1 error correction code.
(3) ECC decoder (IC40-68)
In the ECC decoder block, the sync block segment is
output with the channel coding decoder and the following
processing are carried out.
. Reverse word interleave
. Inverted reverse randomization
. C1 error correction
. Reverse track interleave
. C2 error correction
C1 error correction can correct the error of maximum of 5
bytes in a sync block, and the C2 error correction can
correct the error of a maximum of 26 bytes. Moreover, to
increase the reliability, the successive check is performed
in the decode side (the process of the reverse interleave
and randomization) and in the block side except the error
segment.
(4) Channel coding encoder
The word interleave processed data is converted from 8-bit
data to 9-bit data, and the first 4-byte signal of the sync
block is also added. To distinguish a long bit string
comprising 0 and 1, the tape record signal is converted
from 8 bits to 9 bits, which can improve the reliability of
the record function.
(5) Channel coding decoder
To detect the sync signal in this block, the sync block
segments are classified according to the data. After that,
the signal is converted from 9 to 8 bits (the reverse conver-
sion from 8 to 9 bits), and the single 8-bit unit is returned.
(6) Read/Write circuit
The serial signal from the channel coding encoder (IC12)
is converted by the signal processing of the partial re-
sponse Class 4 (PR (1, 0, _1)) and pre-coded. This signal
is sent to the write amplifier and is written on a tape.
The output signal from the read head is amplified by the
read amplifier and is converted to the digital data after
shaping the waveform by the equalizer, and is decoded by
the partial response Class 4 (PR (1, 0, _1)), then is sent to
the channel coding decoder.
8-1 8-1