Register Descriptions; Jtag Device Identification (Id) Register - Intel PXA27 Series Design Manual

26.5

Register Descriptions

This section describes the registers used in JTAG testing.
26.5.1

JTAG Device Identification (ID) Register

The read-only ID register, defined in
code. No programmable supplementary identification code is provided.
When the idcode instruction is selected, the ID register is selected as the serial path between TDI
and TDO. The 32-bit device identification code is loaded into the ID register during the Capture-
DR state from its parallel inputs.
Table 26-5. JTAG Device Identification (ID) Register
JTAG access only
Bit
31 30 29 28 27 26
Version
Reset † † † †
1 0
Bits Access
31:28
27:12
11:0
† These values reflect the actual production identification and revision numbers embedded in the PXA27x processor.
®
Intel PXA27x Processor Family Design Guide
JTAG Device Identification (ID)
25 24 23 22 21 20 19 18
Part Number
0 1 0 0 1 0 0
Name
The version number changes with each new revision of silicon.
R Version
Processor stepping:
0b0000 = A0
0b0001 = A1
0b0010 = B0
0b0011 = B1
0b0100 = C1
The part number of the PXA27x processor is subject to change:
R Part Number
0b1001_0010_0110_0101 (0x9265)
The JEDEC code is the manufacturer identification number:
R JEDEC Code
0b0000_0001_0011 (0x013)
Table 26-5, is for reading the 32-bit device identification
Register
17 16 15 14 13 12 11
1 1 0 0 1 0 1 0
Description
JTAG Debug
PXA27x Processor
Test Controller
10 9 8 7 6 5 4 3
JEDEC Code
0 0 0 0 0 0 1 0
2 1 0
0 1 1
II:26-15