Analog Devices ADV7850 Hardware Manual page 7

Manual Gain Control ...................................................................................................................................................... 245
9.3.4
Manual Gain Filter Mode ............................................................................................................................................... 247
9.3.5
Automatic Gain Control ................................................................................................................................................. 247
9.3.6
9.3.6.1 Readback Signals from AGC Block ....................................................................................................................................... 249
9.4 CP O B
FFSET LOCK
9.5 CP D P
ATA ATH FOR
Pregain Block ................................................................................................................................................................... 253
9.5.1
9.6 S P
YNC ROCESSED BY
Sync Extracted by Sync Slicer Section ............................................................................................................................. 258
9.6.1
External Sync and Sync from HDMI Section ................................................................................................................. 259
9.6.2
9.6.2.1 Signals Routing to Synchronization Channels ....................................................................................................................... 259
9.6.2.2 XTAL Clock Registering and Glitch Rejection Filter ............................................................................................................ 260
9.6.2.3 Signal Routed to SSPD Blocks .............................................................................................................................................. 261
Final Sync Muxing Stage ................................................................................................................................................. 262
9.6.3
9.7 S
YNCHRONIZATION
Synchronization Source Polarity Detector ...................................................................................................................... 263
9.7.1
9.7.1.1 SSPD Readback Signals ......................................................................................................................................................... 267
Standard Detection and Identification ........................................................................................................................... 271
9.7.2
Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism .................................................................. 274
9.7.3
9.7.3.1 STDI Horizontal Locking Operation ...................................................................................................................................... 274
9.7.3.2 STDI Vertical Locking........................................................................................................................................................... 274
9.7.3.3 STDI Usage............................................................................................................................................................................ 277
9.7.3.4 STDI Readback Values for SD, PR, and HD ......................................................................................................................... 277
9.7.3.5 STDI Readback Values for Graphics Standards .................................................................................................................... 278
9.8 CP O S
UTPUT YNCHRONIZATION
CP Primary Synchronization Signals .............................................................................................................................. 279
9.8.1
HSync Timing Controls ................................................................................................................................................... 280
9.8.2
VSync Timing Controls ................................................................................................................................................... 283
9.8.3
DE Timing Controls ........................................................................................................................................................ 285
9.8.4
FIELD Timing Controls .................................................................................................................................................. 287
9.8.5
HCOUNT Timing Control .............................................................................................................................................. 296
9.8.6
9.9 CP D P
ATA ROCESSING
9.10 CP H
ORIZONTAL
9.11 N C
OISE AND
Measurement Window ............................................................................................................................................... 298
9.11.1
Noise Measurement .................................................................................................................................................... 298
9.11.2
Calibration Measurement .......................................................................................................................................... 299
9.11.3
9.12 F R M
REE UN ODE
Free Run Mode Thresholds ........................................................................................................................................ 299
9.12.1
9.12.1.1 Horizontal Free Run Conditions ....................................................................................................................................... 299
Vertical Run Conditions............................................................................................................................................. 301
9.12.2
Free Run Default Color Output ................................................................................................................................. 303
9.12.3
9.13 CP S ..................................................................................................................................................................................... 304
TATUS
9.14 A G
UTO RAPHICS
Primary Auto Graphics Controls ............................................................................................................................... 305
9.14.1
Graphics Controls ....................................................................................................................................................... 308
9.14.2
10 VBI DATA PROCESSOR .................................................................................................................................................... 310
10.1 VDP C
ONFIGURATION
VDP Default Configuration ....................................................................................................................................... 310
10.1.1
VDP Manual Configuration ...................................................................................................................................... 312
10.1.2
10.2 T S
ELETEXT YSTEM
10.3 VDP D
ECODED
Teletext Readback Registers ....................................................................................................................................... 314
10.3.1
Rev. A May 2012
.............................................................................................................................................................................. 252
A M ................................................................................................................................................ 253
NALOG ODE
CP S ..................................................................................................................................................... 258
ECTION
P C
ROCESSING HANNEL
S P
IGNAL
D C ....................................................................................................................................... 296
ELAY ONTROLS
L S ................................................................................................................................................... 296
OCK TATUS
............................................................................................................................................................. 298
ALIBRATION
............................................................................................................................................................................ 299
M ................................................................................................................................................................ 305
ODE
.................................................................................................................................................................. 310
I ............................................................................................................................................ 313
DENTIFICATION
D R R
ATA EADBACK EGISTERS
M ........................................................................................................................... 262
UX
................................................................................................................. 278
OSITIONING
............................................................................................................................ 314
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ADV7850