Tx Core; Interrupt Architecture Overview; Figure 148: Processing Trilevel Interrupts - Analog Devices ADV7850 Hardware Manual

Tri- Level Sync
Interrupt Initialisation
15.6

TX CORE

This section describes the interrupt support provided for the Tx core of the ADV7850.The Tx interrupts are available on INT1 pin only.

Interrupt Architecture Overview

15.6.1
This section describes the available HDMI Tx interrupts:
• hdcp_authentication_int: indicates if the HDCP protocol was authenticated
• edid_ready_int: indicates if the HDMI receiver EDID is ready for reading
• vsync_int: flags the falling edge on a VSync signal
• rx_sense_int: detects if a HDMI receiver is connected to the HDMI transmitter
• hpd_int: indicates the HDMI transmitter is connected to a HDMI receiver
The interrupt architecture of the Tx core provides two different types of bits:
• Interrupt bits
• Interrupt mask bits
Rev. A May 2012
Enable required Tri - level Interrupts via
Tri - level Interrupt masks.
Registers 0x17 to 0x18 , AFE Map
Enable AFE interrupt. Via
AFE interrupt masks.
Register 0x45[0] to 0x46[0],
IO Map

Figure 148: Processing Trilevel Interrupts

Tri-Level Sync
Interrupt Processing
Interrupt
occurs
Has AFE Interrupt
occurred?
IO Map, Address 43[0].
Yes
Read Required Tri - level
Interrupt Status bits.
AFE Map, Address 0x1B,
0x1C
Clear all Tri-level Interrupt
Status bits.
AFE Map, Address 0x19,
0x1A
React to Tri - level
Interrupt Status
Yes
bits as required.
Clear AFE interrupt .
IO Map, register 0x44 [0]
Is AFE RAW STATUS High
IO Map, Register 0x42[0]
426
No
No Finish
ADV7850