Sdp Synchronization Output Signals; Hsync Timing Configuration - Analog Devices ADV7850 Hardware Manual

sdp_lbox_beg_del[3:0], Addr 90 (SDP), Address 0xDB[3:0]
This control is used to set the letterbox detection begin line versus the default position.
Function
sdp_lbox_beg_del[3:0]
1000 
sdp_lbox_end_del[3:0], Addr 90 (SDP), Address 0xDB[7:4]
This control is used to set the letterbox detection end line versus the default position.
Function
sdp_lbox_end_del[3:0]
1000 
6.18

SDP SYNCHRONIZATION OUTPUT SIGNALS

HSync Timing Configuration

6.18.1
The following controls allow the user to configure the behavior of the HSync on the output pin only:
HSync timing adjustments:
• sdp_hs_beg_adj[11:0]
• sdp_hs_width[11:0]
• sdp_fhe_tog_inv
• sdp_fho_tog_inv
HSync polarity adjustment:
• sdp_hs_pol
sdp_hs_pol, Addr 94 (sdp_IO), Address 0xB1[0]
A control to change polarity of HS/CS.
Function
sdp_hs_pol
0
1 <<
sdp_hs_beg_adj[11:0], Addr 94 (sdp_IO), Address 0x94[3:0]; Address 0x95[7:0]
The sdp_hs_beg_adj[11:0] and sdp_hs_width[11:0] bits allow the user to freely position the HSync signal applied to the output pin
within the video line. The values in the sdp_hs_beg_adj[11:0] and sdp_hs_width[11:0] bits are measured in pixel units from the default
falling edge position of the HSync. Using both values, the user can program both the position and the width of the HSync output signal.
The sdp_hs_beg_adj[11:0] adjusts the leading and trailing edge positions, hence adjusting the HSync pulse. The number applied to the
register offsets the HSync pulse position with respect to the default value. The number is a twos complement value, which allows both
positive and negative edge movement.
Function
sdp_hs_beg_adj[11:0]
0x000 <<
Rev. A May 2012
Description
Letterbox detection aligned with start line of active video. Window starts after VBI data line.
Description
Letterbox detection ends with last active line of video on field
Description
Inverted HS/CS pin polarity
Default HS/CS pin polarity
Description
Default value
125
ADV7850