Sync Stripper Slice Level; D-Terminal Connector; Tri 1-8 Input Resistor Selection; Table 7: D-Terminal Connector Characteristics (Trilevel) - Analog Devices ADV7850 Hardware Manual

Sync Stripper Slice Level

5.8.2
A comparator stage is located after the filter stage. This has programmable thresholds, which offer the user various slice levels that
determine the presence of a valid synchronization pulse. The register
Sync Stripper 1 and Sync Stripper 2.
slice_level[4:0], AFE, Address 0x16[4:0]
This control is used to set the slice level in the synchronization strippers. A smaller value corresponds to a higher slice level.
For a clamp at 300 mV, the slice level is equal to 600 mV - ((slice_level + 1) * 9.375 mV).
Function
slice_level[4:0]
00000
XXXXX
11000 
11111
Several video connectors and cables have signals that are structured as three-level signals. These include the European SCART connector,
which has two such signals; and the Japanese D-connector, which has three. These signals convey much information about the parameters
of the signal being sent. In order for the ADV7850 to use this information, it must slice the voltage levels appearing on TRI1-TRI8.
The following eight pins are capable of slicing a trilevel signal in the ADV7850:
•
TRI1
• TRI2
•
TRI3
• TRI4
•
HS_IN1/TRI5 (known also as TRI5)
• VS_IN2/TRI6 (known also as TRI6)
•
HS_IN2/TRI7 (known also as TRI7)
• VS_IN2/TRI8 (known also as TRI8)

D-Terminal Connector

5.8.3
Table 7 and Table 8 show details of the D-terminal connector used in Japan. The Dataline 1, Dataline 2, and Dataline 3 signals are the
three signals that can be applied to any of the eight TRI inputs. The ADV7850 can process two D-terminal connectors. In this case, six of
the available eight TRI inputs would be utilized.
Level
A
B
C

TRI 1-8 Input Resistor Selection

5.8.4
As can be seen from Table
therefore, are beyond the range of the ADV7850 TRI inputs. The applied signals need to be reduced to fit in the range of the slicers. This is
done by utilizing resistor divider networks at the inputs to TRI1-8.
Rev. A May 2012
Description
Highest slice level
Clamp at 300 mV and slice at 600 mV - ((XXXXX + 1) * 9.375 mV)
Default
Lowest slice level

Table 7: D-Terminal Connector Characteristics (Trilevel)

Minimum
Voltage
0 V
1.4 V
3.5 V

Table 8: D-Terminal Connector Characteristics (Bilevel)

Level
A
B
7, Table 8, Table 9, and Table
slice_level[4:0]
Maximum Pin 8 (Dataline 1)
Voltage
0 V 525 lines
2.4 V 750 lines
5 V 1125 lines
Typical Voltage Pin 9 (Dataline 2)
0 V 59.94i/60i
5 V 59.94p/60p
10, the voltage levels to be sliced exceed the power supplies of the ADV7850 and,
53
is a 5-bit register that sets up slice levels for both
Pin 11 (Dataline 3)
4:3
4:3 letterbox
16:9
ADV7850