Analog Devices ADV7850 Hardware Manual page 282

start_hs[9:0], Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0]
This control is used to shift the position of the leading edge of the HSync output by the CP core. It stores a signed value in a twos
complement format. This control is the number of pixel clocks by which the leading edge of the HSync is shifted (e.g. 0x3FF
corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks towards the active
video).
Function
start_hs[9:0]
0x000 
0x000 to 0x1FF
0x200 to 0x3FF
Examples of how to control the BEGIN of the HSync timing signal:
start_hs[9:0]
0000000000 
0000000001
0100000000
0111111111
1111111111
1011111111
1000000000
Closer to active video
1
Away from active video
2
end_hs[9:0], Addr 44 (CP), Address 0x7C[1:0]; Address 0x7D[7:0]
This control is used to shift the position of the trailing edge of the HSync output by the CP core. It stores a signed value in a twos
complement format. This control is the number of pixel clocks by which the trailing edge of the HSync is shifted (e.g. 0x3FF
corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks towards the active
video).
Function
end_hs[9:0]
0x000 
0x000 to 0x1FF
0x200 to 0x3FF
Rev. A May 2012
Description
Default
Leading edge of HSync shifted towards active video
Leading edge of HSync shifted away from active video
Hex Result
0x000 No move
1
1 x sec shift later than default
0x001
LLC
1
256 x sec shift later than default
0x100
LLC
1
511 x sec shift later than default
0x1FF
LLC
1
1 x sec shift earlier than default
0x3FF
LLC
1
256 x sec shift earlier than default
0x3FE
LLC
1
512 x sec shift earlier than default
0x200
LLC
Description
Default
Trailing edge of HSync shifted towards active video
Trailing edge of HSync shifted away from active video
1
2
282
ADV7850
Note
Default
Minimum →
Maximum →
Minimum ←
Maximum ←