Figure 8: Sdp Clamping Overview - Analog Devices ADV7850 Hardware Manual

The clamping can be divided into two sections:
•
Clamping before the ADC (analog domain): digitally controlled current sources
• Clamping after the ADC (digital domain): digital processing block
The ADCs can digitize an input signal if it resides within the ADC input voltage range of 1.0 V. An input signal with a DC level that is too
large or too small will be clipped at the top or bottom of the ADC range.
The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the
analog-to-digital conversion can take place. After digitization, the digital fine clamp block corrects for any remaining variations in DC
level. Since the DC level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a
fine clamp with high accuracy, otherwise brightness variations can occur.
This section describes the I
sdp_dclp_speed[4:0], Addr 90 (SDP), Address 0x0C[4:0]
This control is used to adjust the speed of digital clamp operation.
Function
sdp_dclp_speed[4:0]
00000
Valid range
All other values
sdp_dclp_speed[4:0] determines the time constant of the digital clamp circuitry. It is important to realize that the digital clamp reacts very
fast to correct immediately any residual DC level error for the active line. The time constant of the digital clamp must be a lot faster than
the one from the analog blocks.
This register also allows the user to freeze the digital clamp loop at any point in time.
By default, the time constant of the digital clamp is adjusted dynamically to suit the currently connected input signal.
sdp_aclp_speed[4:0], Addr 90 (SDP), Address 0x0D[4:0]
This control is used to adjust the speed of the analog clamp operation.
Function
sdp_aclp_speed[4:0]
00000
Valid range
All other values
Rev. A May 2012
C signals used to influence the behavior of the SDP clamping.
2
Description
Freeze digital clamp
1 to 6
Reserved
Description
Freeze analog clamp
1 to 6
Reserved

Figure 8: SDP Clamping Overview

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ADV7850