Isrc Packet Registers; Table 31: Isrc1 Packet Registers - Analog Devices ADV7850 Hardware Manual

InfoFrame
Map Address
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
1 As defined by the HDMI 1.4 specifications
The ACP InfoFrame registers are considered valid if
acp_pckt_raw, IO, Address 0x60[5] (Read Only)
This readback indicates the raw status signal of the audio content protection packet detection signal. This bit resets to 0 after an HDMI
packet detection reset or upon writing to acp_packet_id.
Function
acp_pckt_raw
0 
1

ISRC Packet Registers

7.35.2
Table 31 and Table 32 provide lists of the readback registers available for the ISRC packets. Refer to the HDMI 1.4 specifications for a
detailed explanation of the ISRC packet fields.
InfoFrame
Map Address
0xF2
0xF3
0xF4
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
Rev. A May 2012
R/W Register Name
R acp_pb_0_14
R acp_pb_0_15
R acp_pb_0_16
R acp_pb_0_17
R acp_pb_0_18
R acp_pb_0_19
R acp_pb_0_20
R acp_pb_0_21
R acp_pb_0_22
R acp_pb_0_23
R acp_pb_0_24
R acp_pb_0_25
R acp_pb_0_26
R acp_pb_0_27
R acp_pb_0_28
acp_pckt_raw
Description
No ACP packet received within last 600 ms or since last HDMI packet detection reset
ACP packets received within last 600 ms

Table 31: ISRC1 Packet Registers

R/W Register Name
R/W isrc1_packet_id[7:0]
R isrc1_header1
R isrc1_header2
R isrc1_pb_0_1
R isrc1_pb_0_2
R isrc1_pb_0_3
R isrc1_pb_0_4
R isrc1_pb_0_5
R isrc1_pb_0_6
R isrc1_pb_0_7
R isrc1_pb_0_8
R isrc1_pb_0_9
R isrc1_pb_0_10
R isrc1_pb_0_11
R isrc1_pb_0_12
R isrc1_pb_0_13
R isrc1_pb_0_14
R isrc1_pb_0_15
R isrc1_pb_0_16
R isrc1_pb_0_17
R isrc1_pb_0_18
R isrc1_pb_0_19
Packet Byte No.
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
is set to 1.
Packet Byte No.
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
208
ADV7850
1
1