Power-Down Mode - Analog Devices ADV7850 Hardware Manual

• DDC pads (active pull-up depends on XTAL)
• Reset
The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock
within these sections is not affected by xtal_pdn.
core_pdn allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:
•
CP block
•
SDP block
•
Digital section of the HDMI block
The following sections remain active when core_pdn is set:
• STDI block
• SSPD block
cp_pwrdn, Addr A0 (VFE), Address 0x0C[2]
This control is used to power down the clock to the CP core.
Function
cp_pwrdn
0 
1
xtal_pdn, IO, Address 0x0B[0]
This control is used to power down the xtal in the digital blocks.
Function
xtal_pdn
0 
1
core_pdn, IO, Address 0x0B[1]
This control is used to power down the DPP, CP core and digital sections of the HDMI core.
Function
core_pdn
0 
1
vdp_pdn, Addr A0 (VFE), Address 0x0C[1]
This control is used to power down the VDP. It is recommended to power down the VDP when this feature is not required.
Function
vdp_pdn
0
1 

Power-down Mode

3.2.3
The ADV7850 supports the following power-down modes.
• In power-down mode 1, selected sections and pads are kept active to provide E-EDID and +5 V antiglitch filter functionality.
Rev. A May 2012
Description
Power up clock to CP core.
Power down clock to CP core. VDP, DPP and HDMI blocks not affected.
Description
Power up xtal buffer to digital core
Power down xtal buffer to digital core
Description
Power up DPP, CP, SDP and digital sections of HDMI block.
Power down DPP, CP, SDP and digital sections of HDMI block. STDI and SSPD still active when
core_pdn set.
Description
Power up VDP section
Power down VDP section
30
ADV7850