Pin Description; Figure 3: Adv7850 Pin Configuration; Table 1: Function Descriptions - Analog Devices ADV7850 Hardware Manual

2.8 PIN DESCRIPTION

1 2 3 4
A
GND GND GND RXB_2+
B
ARC_A HPA_A GND RXB_2-
C RXA_C+ RXA_C- CVDD GND
D
RXA_0+ RXA_0- CVDD RXD_5V
E
RXA_1+ RXA_1- CVDD RXC_5V
F RXA_2+ RXA_2- CVDD RXB_5V
G
TVDD TVDD TVDD TVDD
H
EP_MISO EP_MOSI SPDIF_IN RXA_5V
SHARED_
J EP_CSB EP_SCK RESET
EDID
K
GND GND DVDDIO DVDDIO
L
HA_AP5 HA_SCLK INT1 SDA
HA_AP3/
M
HA_AP4 INT2 SCL
INT3
AC_LRCL
N
HA_AP2 HA_AP1 AC_MCLK
K
HA_MCLK
P HA_AP0 AC_SDI AC_SCLK
OUT
R
TTX_SCLK TTX_MOSI TTX_MISO TTX_CSB
T
DVDDIO DVDDIO GND GND
TX_DDC_
U TX_AVDD TX_AVDD GND
SCL
TX_DDC_
V
TX_2+ TX_2- GND
SDA
W
TX_1+ TX_1- GND TX_HPD
Y TX_0+ TX_0- GND GND
AA
TX_C+ TX_C- TX_AVDD GND
AB
TX_PLGND TX_PVDD TX_PLVDD SDVDD
TX_RTER
AC GND TX_VDD33 SDVDD
M
1 2 3 4
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
Rev. A May 2012
5 6 7 8 9
RXB_1+ RXB_0+ RXB_C+ ARC_B TVDD
RXB_1- RXB_0- RXB_C- HPA_B TVDD
VDD_EEP
GND GND GND TVDD
ROM
DDCA_SC DDCA_SD DDCB_SC DDCB_SD
VGA_5V
L A L A
GND TEST1 CVDD
GND GND GND
GND GND GND
VDD GND GND
VDD GND GND
VDD GND GND
VDD GND GND
VDD GND GND
VDD GND GND
VDD GND GND
VDD VDD VDD
A7 A3 A10 BA0 CKE
A9 A5 A1 BA1 WE
A11 A6 A2 CAS RAS
A8 A4 A0 CS CKN
5 6 7 8 9
Mnemonic Description
GND Ground
GND Ground
GND Ground
RXB_2+ Digital Input Channel 2 true of Port B in the HDMI interface.
RXB_1+ Digital Input Channel 1 true of Port B in the HDMI interface.
RXB_0+ Digital Input Channel 0 true of Port B in the HDMI interface.
RXB_C+ Digital input clock true of Port B in the HDMI interface.
ARC_B Single ended Audio Return Channel of Port B in the HDMI interface.
TVDD HDMI termination supply (3.3V)
RXC_2+ Digital Input Channel 2 true of Port C in the HDMI interface.
RXC_1+ Digital Input Channel 1 true of Port C in the HDMI interface.
RXC_0+ Digital Input Channel 0 true of Port C in the HDMI interface.
RXC_C+ Digital input clock true of Port C in the HDMI interface.
10 11 12 13 14
RXC_2+ RXC_1+ RXC_0+ RXC_C+ ARC_C
RXC_2- RXC_1- RXC_0- RXC_C- HPA_C
TVDD TVDD TVDD TVDD TVDD
DDCC_SC DDCC_SD DDCD_SC DDCD_SD
VREG
L A L A
CVDD CVDD CVDD CVDD CVDD
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
GND GND GND GND GND
VDD VDD VDD VDD TEST2
GND DQ6 DQ7 DQ0 DQ8
GND DQ4 DQ5 DQ2 DQ11
VREF SDVDD LDQSN DQ3 DQ10
CK SDVDD LDQS DQ1 DQ9
10 11 12 13 14

Figure 3: ADV7850 Pin Configuration

Table 1: Function Descriptions

20
15 16 17 18 19
GND RXD_2+ RXD_1+ RXD_0+ RXD_C+
GND RXD_2- RXD_1- RXD_0- RXD_C-
GND TVDD TVDD TVDD TVDD
GND VGA_SCL VGA_SDA TVDD AC_AVDD AC_AVDD AC_AVDD
CVDD GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
GND GND GND
UDQS SDVDD SAVDD TRI1 TRI2
HS_IN1/T VS_IN1/T
UDQSN SDVDD GND
RI7 RI8
DQ12 DQ14 GND SYNC1 AVIN3
DQ15 DQ13 GND AVIN1 AVIN2
15 16 17 18 19
ADV7850
20 21 22 23
A
ARC_D GND GND GND
ACMUXO ACMUXO
B
HPA_D GND
UT_R UT_L
ACMUXIN ACMUXIN
GND GND C
_1R _1L
ACMUXIN ACMUXIN
D
_2R _2L
ACMUXIN ACMUXIN
E
GND GND
_3R _3L
ACMUXIN ACMUXIN
PLL_LF GND F
_4R _4L
ACMUXIN ACMUXIN
G
AC_AVDD GND
_5R _5L
VREF_AU
H
GND GND FILTA
DIO
AC_AVDD GND ISET FILTD J
AC_DACO AC_DACO
K
AC_AVDD AC_AVDD
ut_R ut_L
L
AC_AVDD AC_AVDD HPOUT_R HPOUT_L
M
AC_AVDD GND GND GND
N
PVDD PVDD XTALN XTALP
GND GND GND GND P
R
GND GND REFN REFP
T
AVDD AVDD AVDD AVDD
AVIN13 AVIN12 AVIN11 AVIN10 U
V
AVDD AVDD AVDD AVDD
W
GND AVOUT2 AVIN9 AVIN8
GND AVOUT1 SYNC3 AVIN7 Y
HS_IN2/T VS_IN2/T
AA
GND TRI3
RI5 RI6
AB
GND SYNC2 AVIN6 TRI4
GND AVIN4 AVIN5 GND AC
20 21 22 23