Analog Devices ADV7850 Hardware Manual page 452

ADV7850
Figure 102: 720p VS Timing ............................................................................................................................................................................ 293
Figure 103: 1080i VS Timing ........................................................................................................................................................................... 294
Figure 104: 1080p VS Timing .......................................................................................................................................................................... 295
Figure 105: Synchronization Lock Robustness Measurement .................................................................................................................... 297
Figure 106: Free Run Field Length Selection for Channel 1 and Channel 2 ............................................................................................. 303
Figure 107: WSS (625i) Waveform ................................................................................................................................................................. 315
Figure 108: CGMS (525i) Waveform .............................................................................................................................................................. 315
Figure 109: CCAP Waveform and Decoded Data Correlation ................................................................................................................... 316
Figure 110: VITC Waveform and Decoded Data Correlation .................................................................................................................... 317
Figure 111: VDP Interrupt Operation ............................................................................................................................................................ 331
Figure 112: VDP Access Over SPI ................................................................................................................................................................... 331
Figure 113: Audio Block ................................................................................................................................................................................... 333
Figure 114: Audio Codec Analog Inputs Hardware Configuration ........................................................................................................... 333
Figure 115: Audio Codec Mux Output Hardware Configuration .............................................................................................................. 334
Figure 116: High Level Overview of Analog Audio Mux Input/Mux Output Configuration ................................................................ 336
Figure 117: Audio PLL Loop Filter Components ......................................................................................................................................... 337
Figure 118: Audio Codec VREF AUDIO, FILTA and FILTD Configuration .......................................................................................... 338
Figure 119: Audio Codec DAC Output Hardware Configuration ............................................................................................................. 338
Figure 120: Audio Codec Headphone Output Hardware Configuration.................................................................................................. 339
Figure 121: DDR2 BIST Test Architecture .................................................................................................................................................... 346
Figure 122: Functional Block Diagram of HDMI Tx Core.......................................................................................................................... 349
Figure 123: Format of Video Data Input into HDMI Tx Core ................................................................................................................... 356
Figure 124: I C Write Timing if GMP Data ................................................................................................................................................... 361
2
Figure 125: IEC60958 Sub Stream ................................................................................................................................................................... 367
Figure 126: AES3 Stream Format Input to ADV7850 .................................................................................................................................. 367
Figure 127: Timing of Standard I2S Stream Input to ADV7850 ................................................................................................................ 367
Figure 128: Timing for Right-Justified I2S Stream Input to ADV7850 ..................................................................................................... 368
Figure 129: Timing for Left-Justified I2S Stream Input to ADV7850 ........................................................................................................ 368
Figure 130: Timing for I2S Stream in 32-bit Mode ...................................................................................................................................... 368
Figure 131: Timing for I2S Stream in Left or Right-Justified and 32-bit Modes ...................................................................................... 368
Figure 132: Audio Clock Regeneration .......................................................................................................................................................... 370
Figure 133: Definition of Channel Status Bits 20 to 23 ................................................................................................................................ 377
Figure 134: Reading Sink EDID Through ADV7850 ................................................................................................................................... 381
Figure 135: HDCP Software Implementation ............................................................................................................................................... 386
Figure 136: ADV7850 Register Map Access through Main I C Port ......................................................................................................... 388
2
Figure 137: Bus Data Transfer ......................................................................................................................................................................... 389
Figure 138: Read and Write Sequence ............................................................................................................................................................ 389
Figure 139: Current Address Read Sequence ................................................................................................................................................ 390
Figure 140: Internal E-EDID and HDCP Registers Access from Port A ................................................................................................... 390
Figure 141: Internal E-EDID and HDCP Registers Access from Port B ................................................................................................... 390
Figure 142: Internal E-EDID and HDCP Registers Access from Port C ................................................................................................... 391
Figure 143: Internal E-EDID and HDCP Registers Access from Port D .................................................................................................. 391
Figure 144: Level and Edge-sensitive Raw, Status and Interrupt Generation ........................................................................................... 396
Figure 145: AVI_INFO_RAW and AVI_INFO_ST Timing ....................................................................................................................... 397
Figure 146: NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing .............................................................................................. 397
Figure 147: Suggested Method of Handling afe_interrupt .......................................................................................................................... 401
Figure 148: Processing Trilevel Interrupts ..................................................................................................................................................... 426
Figure 149: Recommended Power Supply Decoupling ................................................................................................................................ 429
Figure 150: Recommended Power Up Sequence .......................................................................................................................................... 430
Figure 151: Crystal Circuit ............................................................................................................................................................................... 431
Figure 152: ADV7850 Analog Input Connections (1) ................................................................................................................................. 433
Figure 153: ADV7850 Analog Input Connections (2) ................................................................................................................................. 434
Rev. A May 2012 452