Analog Devices Advantiv ADV7619 Hardware User's Manual
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Analog Devices Advantiv ADV7619 Hardware User's Manual

Analog Devices Advantiv ADV7619 Hardware User's Manual

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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Dual Port Xpressview™ Advantiv HDMI Receiver Functionality and Features

SCOPE

This user guide provides a detailed description of the Advantiv™ ADV7619 functionality and features.

DISCLAIMER

Information furnished by Analog Devices, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
XTALP
DPLL
XTALN
SCL
SDA
CS
CEC
CEC
CONTROLLER
RXA_5V
5V DETECT
RXB_5V
AND HPD
HPA_A/INT2
CONTROLLER
HPA_B
DDCA_SDA
EDID
DDCA_SCL
REPEATER
DDCB_SDA
CONTROLLER
DDCB_SCL
PLL
RXA_C±
RXA_0±
EQUALIZER
RXA_1±
RXA_2±
RXB_C±
PLL
RXB_0±
RXB_1±
EQUALIZER
RXB_2±
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
CONTROL
INTERFACE
I
2
C
CONTROL
AND DATA
HDCP
EEPROM
HDCP
ENGINE
SAMPLER
SAMPLER
Figure 1. Functional Block Diagram
Rev. A | Page 1 of 204
3Gbs VIDEO PATH
BACKEND
COLOR SPACE
CONVERSION
HDMI
PROCESSOR
COMPONENT
PROCESSOR
A
DATA
B
PREPROCESSOR
C
AND COLOR
SPACE
CONVERSION
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
Hardware User Guide
12
12
12
12
INTERRUPT
CONTROLLER
(INT1, INT2)
MUTE
AUDIO
PROCESSOR
ADV7619
UG-237
P0 TO P11
P12 TO P23
P24 TO P35
P36 TO P47
LLC
HS/CS
VS/FIELD/ALSB
DE
INT1
AP1/I2S_TDM
AP2
AP3
AP4
AP5
SCLK/INT2
MCLK/INT2
AP0

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  • Page 1: Scope

    Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

  • Page 2: Table Of Contents

    UG-237 Hardware User Guide TABLE OF CONTENTS Scope ....................1 Fast Switching and Background Port Selection ...... 39 Disclaimer ..................1 TMDS Clock Activity Detection ..........40 Revision History ................3 HDMI/DVI Status Bits .............. 41 Using the ADV7619 Hardware User Guide ........4 Video 3D Detection ..............

  • Page 3: Revision History

    Hardware User Guide UG-237 CP Data Path for HDMI Modes ..........125 Interrupt Pins ................170 Sync Processed by CP Section ..........129 Description of Interrupt Bits ........... 173 CP Output Synchronization Signal Positioning ....136 Additional Explanations ............174 CP HDMI Controls ..............

  • Page 4: Using The Adv7619 Hardware User Guide

    UG-237 Hardware User Guide USING THE ADV7619 HARDWARE USER GUIDE NUMBER NOTATIONS Table 1. Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V).
  • Page 5 Hardware User Guide UG-237 Acronym/Abbreviation Description Key selection vector. Line locked clock. Least significant bit. L-PCM Linear pulse coded modulated. Mbps Megabit per second. MPEG Moving picture expert group. Millisecond. Most significant bit. No connect. One-time programmable. Pj’ HDCP enhanced link verification response. Refer to HDCP documentation. Ri’...

  • Page 6: Field Function Descriptions

    UG-237 Hardware User Guide FIELD FUNCTION DESCRIPTIONS Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I C map, the register location within the I C map, and a detailed description of the field.

  • Page 7: Introduction To The Adv7619

    The ADV7619 also integrates an CEC controller that supports the capability discovery and control (CDC) feature. The ADV7619 incorporates Xpressview™ fast switching on both input HDMI ports. Using Analog Devices’ hardware-based HDCP engine that minimizes software overhead, Xpressview™ technology allows fast switching between both HDMI input ports in less than 1 second.

  • Page 8: Changes To Video Output Formats Section

    UG-237 Hardware User Guide Component Video Processing • Support video formats only up to 1080p 36-bit deep color and graphics up to UXGA 10-bit • An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb •...

  • Page 9: Functional Block Diagram

    Hardware User Guide UG-237 Additional Features • HS, VS, FIELD, and DE output signals with programmable position, polarity, and width • Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2 •...

  • Page 10: Pin Configuration And Function Descriptions

    UG-237 Hardware User Guide PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 CVDD VS/FIELD/ALSB RXA_C– RXA_C+ TVDD DVDDIO RXA_0– RXA_0+ TVDD RXA_1– RXA_1+ TVDD ADV7619 RXA_2– RXA_2+ TOP VIEW (Not to Scale) CVDD TEST1 DVDD TEST2 DVDD CVDD RXB_C– DVDDIO RXB_C+ TVDD RXB_0–...
  • Page 11 Hardware User Guide UG-237 Pin No. Mnemonic Type Description TVDD Power Terminator Supply Voltage (3.3 V). RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
  • Page 12 UG-237 Hardware User Guide Pin No. Mnemonic Type Description DVDD Power Digital Core Supply Voltage (1.8 V). Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port.

  • Page 13: Changes To Pin 113 Description

    Hardware User Guide UG-237 Pin No. Mnemonic Type Description Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output Digital video Video Pixel Output Port. output DVDDIO Power...
  • Page 14 UG-237 Hardware User Guide Pin No. Mnemonic Type Description HPA_B Miscellaneous Hot Plug Assert signal output for HDMI Port B. digital RXB_5V HDMI input 5 V Detect Pin for Port B in the HDMI Interface. DDCA_SCL HDMI input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. DDCA_SDA HDMI input HDCP Slave Serial Data Port A.

  • Page 15: Global Control Registers

    Hardware User Guide UG-237 GLOBAL CONTROL REGISTERS The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7619. ADV7619 REVISION IDENTIFICATION RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only) Chip revision code.
  • Page 16 UG-237 Hardware User Guide CORE_PDN CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections: • CP block • Digital section of the HDMI block CORE_PDN, IO, Address 0x0B[1] A power-down control for the DPP, CP core, and digital sections of the HDMI core. Function CORE_PDN Description...

  • Page 17: Global Pin Control

    Hardware User Guide UG-237 Entering Power-Down Mode 0 via Software The ADV7619 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This method allows an external processor to put the system in which the ADV7619 is integrated into standby mode. In this case, the CP and HDMI cores of the ADV7619 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0 through the POWER_DOWN bit.
  • Page 18 UG-237 Hardware User Guide TRI_PIX This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[35:0] is tristated. TRI_PIX, IO, Address 0x15[1] A control to tristate the pixel data on the pixel pins, P[47:0]. Function TRI_PIX Description...
  • Page 19 Hardware User Guide UG-237 TRI_AUDIO, IO, Address 0x15[4] A control to tristate the audio output interface pins (AP0, AP1/I2S_TDM, AP2, …, AP5). Function TRI_AUDIO Description Audio output pins active 1 (default) Tristates audio output pins Drive Strength Selection DR_STR It may be desirable to strengthen or weaken the drive strength of the output drivers for Electromagnetic Compatibility (EMC) and crosstalk reasons.
  • Page 20 UG-237 Hardware User Guide Output Synchronization Selection VS_OUT_SEL, IO, Address 0x06[7] A control to select the VSync or FIELD signal to be output on the VS/FIELD/ALSB pin. Function VS_OUT_SEL Description Selects FIELD output on VS/FIELD/ALSB pin 1 (default) Selects VSync output on VS/FIELD/ALSB pin F_OUT_SEL, IO, Address 0x05[4] A control to select the DE or FIELD signal to be output on the DE pin.
  • Page 21 Hardware User Guide UG-237 INV_F_POL, IO, Address 0x06[3] A control to select the polarity of the DE signal. Function INV_F_POL Description 0 (default) Negative FIELD/DE polarity Positive FIELD/DE polarity Digital Synthesizer Controls The ADV7619 features two digital encoder synthesizers that generate the following clocks: •...

  • Page 22: Primary Mode And Video Standard

    UG-237 Hardware User Guide PRIMARY MODE AND VIDEO STANDARD Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7619. There are two primary modes for the ADV7619: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with PRIM_MODE[3:0].
  • Page 23 Hardware User Guide UG-237 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment 0101 HDMI-COMP 000000 SD 1×1 525i 720 × 480 HDMI receiver support (Component video) 000001 SD 1×1 625i 720 × 576 000010 SD 2×1 525i 720 ×...

  • Page 24: Hdmi Decimation Modes

    UG-237 Hardware User Guide PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment 1010 Reserved xxxxxx Reserved Reserved 1011 Reserved xxxxxx Reserved Reserved 1100 Reserved xxxxxx Reserved Reserved 1101 Reserved xxxxxx Reserved Reserved 1110 Reserved xxxxxx Reserved Reserved 1111 Reserved xxxxxx...

  • Page 25: Recommended Settings For Hdmi Inputs

    Hardware User Guide UG-237 RECOMMENDED SETTINGS FOR HDMI INPUTS This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection Video ID Code described in the 861 specification. Table 7 provides the recommended settings for the following registers: ...
  • Page 26 UG-237 Hardware User Guide Recommended Settings if Recommended Settings if Free Run Not Used or Free Video ID Codes Pixel Free Run Used and Run Used and (861 Specification) Formats Repetition DIS_AUTOPRAM_BUFFER = 0 DIS_AUTO_PARAM_BUFFER = 1 37, 38 2880 × 576p @ 60 Hz PRIM_MODE = 0x5 PRIM_MODE = 0x6 VID_STD = 0xA...

  • Page 27: Pixel Port Configuration

    Hardware User Guide UG-237 PIXEL PORT CONFIGURATION The ADV7619 has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. The ADV7619 can provide output modes up to 36 bits for video with pixel clock frequency below 170 MHz, and 48 bits for video with pixel rates above 170 MHz.

  • Page 28: Ddr Output Interface

    UG-237 Hardware User Guide Bus Rotation and Reordering Controls Bus reordering controls are available for ADV7619. OP_CH_SEL[2:0] allows the three output buses to be rearranged, thus providing six different output possibilities. OP_CH_SEL[2:0], IO, Address 0x04[7:5] A control to select the configuration of the pixel data bus on the pixel pins. Refer to the pixel port configuration for full information on pixel port modes and configuration settings.

  • Page 29: Llc Controls

    Hardware User Guide UG-237 LLC CONTROLS The ADV7619 has a number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can be inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve suitable setup and hold times for any back end device.

  • Page 30: Hdmi Receiver

    UG-237 Hardware User Guide HDMI RECEIVER HPA_A/INT2 HPA_B TO INTERRUPT 5V DETECT CONTROLLER AND HPA CONTROLLER RXA_5V DATA RXB_5V VIDEO OUTPUT DEEP COLOR FORMATTER CONVERSION (3Gbs VIDEO PATH) CONTROLLER DATA EDID/ DDCA_SDA/DDCA_SC L TO DATA 4:2:2 TO 4:4:4 REPEATER PREPROCESSOR DDCB_SDA/DDCB_SC L CONVERSION CONTROLLER...

  • Page 31: Hot Plug Assert

    Hardware User Guide UG-237 Function FILT_5V_DET_DIS Description 0 (default) Enabled Disabled Note: If the +5 V pins are not used and are left unconnected, the +5 V detect circuitry must be disconnected from the HDMI reset signal by setting DIS_CABLE_DET_RST to 1. This avoids holding the HDMI section in reset. FILT_5V_DET_TIMER[6:0], Addr 68 (HDMI), Address 0x56[6:0] This control is used to set the timer for the digital glitch filter on the HDMI +5 V detect inputs.
  • Page 32 UG-237 Hardware User Guide HPA_AUTO_INT_EDID[1:0], Addr 68 (HDMI), Address 0x6C[2:1] This control selects the type of automatic control on the HPA output pins. This bit has no effect when HPA_MANUAL is set to 1. Function HPA_AUTO_INT_EDID[1:0] Description HPA of an HDMI port asserted high immediately after internal EDID activated for that port. HPA of a specific HDMI port deasserted low immediately after internal E-EDID is de-activated for that port.

  • Page 33: E-Edid/Repeater Controller

    Hardware User Guide UG-237 HPA_STATUS_PORT_A, IO, Address 0x21[3] (Read Only) Readback of HPA status for Port A. Function HPA_STATUS_PORT_A Description 0 (default) +5 V not applied to HPA_A pin by chip +5 V applied to HPA_A pin by chip HPA_STATUS_PORT_B, IO, Address 0x21[2] (Read Only) Readback of HPA status for Port B.
  • Page 34 UG-237 Hardware User Guide EDID_A_ENABLE, Addr 64 (Repeater), Address 0x74[0] Enables I C access to the internal EDID RAM from DDC Port A. Function EDID_A_ENABLE Description 0 (default) Disables E-EDID for Port A Enables E-EDID for Port A EDID_B_ENABLE, Addr 64 (Repeater), Address 0x74[1] Enables I C access to the internal EDID RAM from DDC Port B.

  • Page 35: Transitioning Of Power Modes

    Hardware User Guide UG-237 TRANSITIONING OF POWER MODES If the part starts in Power-Down Mode 0 and then transitions into a different power mode (that is, Power-Down Mode 1 or normal operation mode), the information in the internal E-EDID is not overwritten. The internal E-EDID remains active on the HDMI port for which the E-EDID has been accessed.

  • Page 36: Structure Of Internal E-Edid For Port B

    UG-237 Hardware User Guide STRUCTURE OF INTERNAL E-EDID FOR PORT B This section describes the structure of the internal E-EDID accessible through the DDC bus of Port B. The internal E-EDID is enabled for Port B by setting the EDID_B_ENABLE bit to 1. The image of the internal E-EDID that is accessed on the DDC bus of Port B corresponds to the data image contained in the internal E-EDID RAM except for the SPA, SPA location, and the checksum of the E-EDID block where the SPA is located.
  • Page 37 Hardware User Guide UG-237 PORT B E-EDID STRUCTURE 0x1FF BLOCK 3 CHECKSUM 0x1FF 0x1FE INTERNAL EDID RAM BLOCK 3 0x180 0x180 0x17F BLOCK 2 CHECKSUM 0xFF PORT_B_CHECKSUM[7:0] REPEATER MAP, REG 0x70, REG 0x71 0x17E 0xFE INTERNAL EDID RAM SPA_LOCATION[8:0]+2 BLOCK 2 SPA_PORT_B[15:0] REPEATER MAP, REG 0x70, REG 0x71 SPA_LOCATION[8:0]–1...
  • Page 38 UG-237 Hardware User Guide Notes • When internal E-EDID is required for Port B, the SPA along with its location address in the E-EDID must be programmed in the Repeater Map, registers SPA_PORT_B[15:0]and SPA_LOCATION[7:0], respectively. • After EDID_B_ENABLE is set to 1, the ADV7619 EDID/Repeater controller computes the four checksums of the E-EDID image for Port B.

  • Page 39: Tmds Equalization

    Hardware User Guide UG-237 TMDS EQUALIZATION The ADV7619 incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at long lengths and higher frequencies. The ADV7619 is capable of equalizing for cable lengths up to 30 meters and for pixel clock frequencies up to 300 MHz.

  • Page 40: Tmds Clock Activity Detection

    UG-237 Hardware User Guide  BG_LINE_WIDTH[12:0]  BG_TOTAL_FIELD_HEIGHT[12:0]  BG_FIELD_HEIGHT[12:0]  BG_HDMI_INTERLACED BG_MEAS_PORT_SEL[2:0], Addr 68 (HDMI), Address 0x00[5:3] BG_MEAS_PORT_SEL[2:0] selects a background port on which HDMI measurements are to be made and provided in the background measurement registers. The port in question must be set as a background port in order for this setting to be effective. There is no conflict if this matches the port selected by HDMI_PORT_SELECT[2:0].

  • Page 41: Hdmi/Dvi Status Bits

    Hardware User Guide UG-237 TMDS_CLK_B_RAW, IO, Address 0x6A[3] (Read Only) Raw status of Port B TMDS clock detection signal. Function TMDS_CLK_A_RAW Description 0 (default) No TMDS clock detected on Port B TMDS clock detected on Port B Important • The clock detection flag is valid if the part is powered up or in Power Down Mode 1. Refer to Power-Down Mode 1 section. •...

  • Page 42: Video 3D Detection

    UG-237 Hardware User Guide BG_HDMI_MODE, Addr 68 (HDMI), Address 0xEB[0] (Read Only) A readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream. Function BG_HDMI_MODE Description 0 (default) DVI mode detected HDMI mode detected VIDEO 3D DETECTION Status of 3D Video is available through VIDEO_3D_RAW bit.
  • Page 43 Hardware User Guide UG-237 BG_TMDSFREQ[8:0] , Addr 68 (HDMI), Address 0xE0[7:0]; Address 0xE1[7] (Read Only) This register provides a precision integer TMDS frequency measurement on the background port selected by BG_MEAS_PORT_SEL[2:0] . The value provided is the result of a single measurement of the TMDS PLL frequency in MHz. This value is updated when an update request is made via the BG_MEAS_REQ control bit.
  • Page 44 UG-237 Hardware User Guide START ENABLE TMDS_CLK_X_ST INTERRUPT FOR THE HDMI PORTS THAT ARE USED ENABLE TMDS_PLL_LCK_ST INTERRUPT ENABLE NEW_TMDS_FRQ_ST INTERRUPT TMDS FREQUENCY READ BACK NOT VALID OR STABLE TMDS_CLK_X_RA W SET? READ THE TMDS FREQUENCY TMDS_PLL_LCK_R TMDSFREQ AW SET? CLEAR TMDS_CLK_X_ST BY TMDS_CLK_X_ST SETTING TMDS_CLK_X_CLR TO 1...

  • Page 45: Deep Color Mode Support

    Hardware User Guide UG-237 DEEP COLOR MODE SUPPORT The ADV7619 supports HDMI streams with 24 bit per sample and deep color modes of 30 or 36 bits per sample. The addition of a video FIFO (refer to the Video FIFO section) allows for the robust support of these modes. The deep color mode information that the ADV7619 extracts from the general control packet can be read back from DEEP_COLOR_ MODE[1:0].

  • Page 46: Video Fifo

    UG-237 Hardware User Guide Function BG_DEEP_COLOR_MODE[1:0] Description 00 (default) 8-bit color per channel 10-bit color per channel 12-bit color per channel 16-bit color per channel (not supported) VIDEO FIFO The ADV7619 contains a FIFO located between the incoming TMDS data and the CP core (refer to Figure 10). Data arriving over the HDMI link will be at 1X for non-deep color mode (8 bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36, and 48 bits, respectively).

  • Page 47: Pixel Repetition

    Hardware User Guide UG-237 Function DCFIFO_LOCKED Description 0 (default) Video FIFO is not locked. Video FIFO had to resynchronize between previous two Vsyncs. Video FIFO is locked. Video FIFO did not have to resynchronize between previous two Vsyncs. DCFIFO_RECENTER , Addr 68 (HDMI), Address 0x5A[2] (Self-Clearing) A reset to recenter the video FIFO.
  • Page 48 UG-237 Hardware User Guide Function HDMI_PIXEL_REPETITION[3:0] Description 0101 6× 0110 7× 0111 8× 1000 9× 1001 10× 1010 to 1111 Reserved DEREP_N_OVERRIDE , Addr 68 (HDMI), Address 0x41[4] This control allows the user to override the pixel repetition factor. The ADV7619 then uses DEREP_N instead of HDMI_PIXEL_REPETITION[3:0] to discard video pixel data from the incoming HDMI stream.

  • Page 49: Hdcp Support

    Hardware User Guide UG-237 FORCE_YCRCB_422 , Addr 68 (HDMI), Address 0x47[4] Forces a 4:2:2 interpretation of the video contents, regardless of the description in the AVI infoframe. This bit is only valid if FORCE_YCRCB_444 is zero. Function FORCE_YCRCB_422 Description 0 (default) Not forced Forced HDCP SUPPORT...
  • Page 50 UG-237 Hardware User Guide Internal HDCP Key OTP ROM The ADV7619 features an on-chip nonvolatile memory that is preprogrammed with a set of HDCP keys. HDCP Keys Access Flags The ADV7619 accesses the internal HDCP key OTP ROM (also referred to as HDCP ROM) on two different occasions: •...
  • Page 51 Hardware User Guide UG-237 START (AKSV UPDATE FROM TRANSMITTER) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV, HDCP KEYS AND CHECKSUM CS2 FROM HDCP PROM DERIVE CHECKSUM CS2' FROM KSV AND HDCP KEYS HDCP_KEY_ERROR = 1 CS1 = CS1' DERIVE LINK VERIFICATION Ri' UPDATE BKSV AND Ri' IN HDCP RESGISTERS HDCP_KEY_READ = 1...

  • Page 52: Hdmi Synchronization Parameters

    UG-237 Hardware User Guide HDCP_RI_EXPIRED , Addr 68 (HDMI), Address 0x04[3] (Read Only) Readback high when a calculated Ri has not been read by the source TX, on the active port. It remains high until next Aksv update. Function HDCP_RI_EXPIRED Description 0 (default) Calculated Ri has been read by the source TX...
  • Page 53 Hardware User Guide UG-237 DE_REGEN_LCK_RAW , IO, Address 0x6A[0] (Read Only) Raw status of the DE regeneration lock signal. Function DE_REGEN_LCK_RAW Description 0 (default) DE regeneration block has not been locked. DE regeneration block has been locked to the incoming DE signal. TOTAL_LINE_WIDTH[13:0] , Addr 68 (HDMI), Address 0x1E[5:0];...
  • Page 54 UG-237 Hardware User Guide DATA ENABLE HSYNC NOTE: TOTAL NUMBER OF PIXELS PER LINE ACTIVE NUMBER OF PIXELS PER LINE HSYNC FRONT PORCH WIDTH IN PIXEL UNIT HSYNC WIDTH IN PIXEL UNIT HSYNC BACK PORCH WIDTH IN PIXEL UNIT Figure 13. Horizontal Timing Parameters Background Port Horizontal Filter Measurements The HDMI horizontal filter performs the measurements described in this section on the HDMI port selected by BG_MEAS_PORT_SEL[2:0] .
  • Page 55 Hardware User Guide UG-237 Vertical Filters and Measurements The ADV7619 integrates a HDMI vertical filter which performs measurements on the VSync of the HDMI stream on the selected port. The ADV7619 also performs vertical measurements on the background port as selected by BG_MEAS_PORT_SEL[2:0] .These measurements are available in the HDMI map and can be used to determine the resolution of the incoming video data streams.
  • Page 56 UG-237 Hardware User Guide FIELD0_VS_PULSE_WIDTH[13:0] , Addr 68 (HDMI), Address 0x2E[5:0]; Address 0x2F[7:0] (Read Only) Field 0 VSync width is a vertical synchronization measurement. The unit for this measurement is half lines. This measurement is valid only when the vertical filter has locked. Function FIELD0_VS_PULSE_WIDTH[13:0] Description...
  • Page 57 Hardware User Guide UG-237 FIELD1_VS_FRONT_PORCH[13:0] , Addr 68 (HDMI), Address 0x2C[5:0]; Address 0x2D[7:0] (Read Only) Field 1 VSync front porch width is a vertical synchronization measurement. The unit of this measurement is half lines. This measurement is valid only when the vertical filter has locked. Field 1 measurements are valid when HDMI_INTERLACED is set to 1. Function FIELD1_VS_FRONT_PORCH[13:0] Description...

  • Page 58: Audio Control And Configuration

    UG-237 Hardware User Guide BG_TOTAL_FIELD_HEIGHT[12:0] , Addr 68 (HDMI), Address 0xE8[4:0]; Address 0xE9[7:0] (Read Only) Background port total field height is a vertical synchronization measurement for the background HDMI port determined by BG_MEAS_PORT_SEL[2:0]. The value represents the total number of lines in a field and is updated when an update request is made via the BG_MEAS_REQ control bit.
  • Page 59 Hardware User Guide UG-237 TMDS CLOCK AUDIO DPLL MCLK 128fs ACR PACKET DATA AUDIO DELAY RAMPED AUDIO DATA TMDS CLOCK AUDIO FIFO LINE MUTE/UNMUTE RECONSTRUCTION, PACKET PROCESSOR SERIALIZATION AND (DISPATCH BLOCK) MUXING TO DPP DATA FROM HDCP VIDEO DATA BLOCK SCLK ENGINE/MASK CHANNEL STATUS...

  • Page 60: Audio Fifo

    UG-237 Hardware User Guide Table 8. Selectable Coast Conditions HDMI Map Corresponding Status Bit Name Address Description Registers(s) AC_MSK_VCLK_CHNG 0x13[6] When set to 1, audio DPLL coasts if TMDS clock has any VCLK_CHNG_RAW irregular/missing pulses AC_MSK_VPLL_UNLOCK 0x13[5] When set to 1, audio DPLL coasts if TMDS PLL unlocks TMDS_PLL_LOCKED AC_MSK_NEW_CTS 0x13[3]...

  • Page 61: Audio Packet Type Flags

    Hardware User Guide UG-237 Function FIFO_OVERFLO_RAW Description 0 (default) Audio FIFO has not overflowed. Audio FIFO has overflowed. FIFO_NEAR_UFLO_RAW, IO, Address 0x83[0] (Read Only) Status of audio FIFO near underflow interrupt signal. When set to 1, it indicates the audio FIFO is near underflow as the number of FIFO registers containing stereo data is less or equal to value set in AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD.
  • Page 62 UG-237 Hardware User Guide AUDIO_SAMPLE_PCKT_DET , Addr 68 (HDMI), Address 0x18[0] (Read Only) Audio sample packet detection bit. This bit resets to zero on the 11th HSync leading edge following an audio packet if a subsequent audio sample packet has not been received or if a DSD, DST, or HBR audio packet sample packet has been received. Function AUDIO_SAMPLE_PCKT_DET Description...

  • Page 63: Audio Output Interface

    Hardware User Guide UG-237 START ENABLE THE AUDIO_MODE_CHNG_ST INTERRUPT AUDIO_MODE_CH NG_ST INTERRUPT? SET AUDIO_MODE_CHNG_CLR TO 1 NO AUDIO SAMPLE PACKETS ARE AUDIO SAMPLE PACKETS ARE AUDIO_SAMPLE BEING RECEIVED BEING RECEIVED PCKT_DET? NO DSD PACKETS ARE DSD PACKETS ARE BEING RECEIVED DSD_PACKET_DET? BEING RECEIVED NO DST PACKETS ARE...
  • Page 64 UG-237 Hardware User Guide Table 10. Default Audio Output Pixel Port Mapping Output Pixel Port S/SPDIF Interface DSD Interface SPDIF0 DSD0A AP1/I2S_TDM I2S0/SDPIF0/I2S_TDM DSD0B I2S1/SDPIF1 DSD1A I2S2/SPDIF2 DSD1B I2S3/SPDIF3 DSD2A LRCLK DSD2B Note that it is possible to tristate the audio pins using the global controls, as described in the Tristate Audio Output Drivers section. It is possible to output AP0 signal (SPDIF0) to the AP1/I2S_TDM pin using MUX_SPDIF_TO_I2S_ENABLE.
  • Page 65 Hardware User Guide UG-237 Table 12. Audio Mappings for I2S_SPDIF_MAP_ROT = 00, I2S_SPDIF_MAP_INV = 1 Output Pixel Port I2S/SPDIF Interface AP1/I2S_TDM I2S3/SDPIF3 I2S2/SDPIF2 I2S1/SDPIF1 I2S0/SDPIF0 I2SBITWIDTH[4:0] , Addr 68 (HDMI), Address 0x03[4:0] A control to adjust the bit width for right justified mode on the I S interface.
  • Page 66 UG-237 Hardware User Guide • A stream conforming to the IEC60958 specification when the part receives audio sample packets with L-PCM encoded data (refer to Figure 22). • An AES3 stream if the I2SOUTMODE[1:0] control is set to 0x3 (refer to Figure 23 and Figure 24). Note that AES3 is also referred to as raw SPDIF.
  • Page 67 Hardware User Guide UG-237 LEFT RIGHT 32 CLOCK SLOTS 32 CLOCK SLOTS Figure 21. Timing Audio Data Output in Left Justified Mode SYNC AUDIO SAMPLE WORD PREAMBLE VALIDITY FLAG USER DATA CHANNEL STATUS PARITY BIT Figure 22. IEC 60958 Subframe Timing Diagram DATA VALIDITY FLAG ZERO PADDING...
  • Page 68 UG-237 Hardware User Guide LRCLK 256 SCLKs SCLK 32 SCLKs SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 1 RIGHT 1 LEFT 2 RIGHT 2 LEFT 3 RIGHT 3 LEFT 4 RIGHT 4 LRCLK SCLK...
  • Page 69 Hardware User Guide UG-237 DSD_MAP_ROT[2:0] and DSD_MAP_INV are independent controls. Any combination of values is therefore allowed for DSD_MAP_ROT[2:0] and DSD_MAP_INV. Table 15 and Table 16 show examples of mappings for the DSD signals. Table 15 Audio Mapping for DSD_MAP_ROT = 00, DSD_MAP_INV = 0 (Default) Output Pixel Port Name DSD Interface DSD0A...
  • Page 70 UG-237 Hardware User Guide HBR Interface and Output Controls The ADV7619 can receive HBR audio stream packets. The ADV7619 outputs HBR data over four of the audio output pins in any of the following formats: • An SDPIF stream conforming to the IEC60958 specification (refer to Figure 22). The following configuration is required to output an SPDIF stream on the HBR output pins: •...

  • Page 71: Mclkout Setting

    Hardware User Guide UG-237 MUX_HBR_OUT , Addr 68 (HDMI), Address 0x01[1] A control to manually select the audio output interface for HBR data. Valid when OVR_MUX_HBR is set to 1. Function MUX_HBR_OUT Description 0 (default) Override by outputting I S data Override by outputting SPDIF data MCLKOUT SETTING The frequency of audio master clock MCLKOUT is set using the MCLK_FS_N[2:0] register, as shown in Equation 3, in the relationship...
  • Page 72 UG-237 Hardware User Guide • Audio mute controller takes in event detection signals that can be used to determine when an audio mute is needed. The controller generates a mute signal to the ramped audio block and a coast signal to the digital PLL generating the audio clock. •...
  • Page 73 Hardware User Guide UG-237 The ADV7619 internally unmutes the audio if the following three conditions (listed in order of priority) are met: • Mute conditions are inactive. • NOT_AUTO_UNMUTE is set to 0. • Audio unmute counter has finished counting down or is disabled. Notes •...
  • Page 74 UG-237 Hardware User Guide Function WAIT_UNMUTE[2:0] Description 000 (default) Disables/cancels delayed unmute. Audio unmutes directly after all mute conditions become inactive. Unmutes 250 ms after all mute conditions become inactive. Unmutes 500 ms after all mute conditions become inactive. Unmutes 750 ms after all mute conditions become inactive. Unmutes 1 sec after all mute conditions become inactive.
  • Page 75 Hardware User Guide UG-237 Audio Mute Signal The ADV7619 can output an audio mute signal that can be used to control the muting in a back end audio device processing the audio data output by the ADV7619 (for example, DSP). The audio mute signal is output on the INT1 pin by setting EN_UMASK_RAW_INTRQ to 1.

  • Page 76: Audio Clock Regeneration Parameters

    UG-237 Hardware User Guide Function MT_MSK_PARITY_ERR Description 1 (default) Audio mute occurs if an audio sample packet is received with an incorrect parity bit AUDIO CLOCK REGENERATION PARAMETERS The ADV7619 recreates an internal audio master clock using audio clock regeneration (ACR) values transmitted by the HDMI source. ACR Parameters Readbacks The registers N and CTS can be read back from the HDMI map.

  • Page 77: Channel Status

    Hardware User Guide UG-237 CTS_CHANGE_THRESHOLD[5:0] , Addr 68 (HDMI), Address 0x10[5:0] Sets the tolerance for change in the CTS value. This tolerance is used for the audio mute mask MT_MSK_NEW_CTS and the HDMI status bit CTS_PASS_THRSH_RAW and the HDMI interrupt status bit CTS_PASS_THRSH_ST. This register controls the amounts of LSBs that the CTS can change before an audio mute, status change or interrupt is triggered.
  • Page 78 UG-237 Hardware User Guide START ENABLE THE CS_DATA_VALID_ST INITIALIZATION INTERRUPT CS_DATA_VALID_S T SET TO 1? CHECK IF THE CS_DATA_VALID SET CS_DATA_VALID_CLR TO 1 INTERRUPT HAS TRIGGERED CS_DATA_VALID_R AW SET TO 1? READ THE CHANNEL STATUS BITS IN THE CHANNEL STATUS BITS PREVIOUSLY HDMI MAP 0x36 TO 0x3A READ ARE NOT VALID CS_DATA_VALID_S...
  • Page 79 Hardware User Guide UG-237 CS_DATA[1], PCM/non-PCM Audio Sample, HDMI Map, Address 0x36[1] Function CS_DATA[1] Description 0 (default) Audio sample word represents linear PCM samples Audio sample word used for other purposes CS_DATA[2], Copyright, HDMI Map, Address 0x36[2] Function CS_DATA[2] Description 0 (default) Software for which copyright is asserted Software for which no copyright is asserted...

  • Page 80: Changes To Cs_Data[27:24], Sampling Fequency, Hdmi Map, Address 0X39[3:0] Section

    UG-237 Hardware User Guide Sampling and Frequency Accuracy The sampling frequency and clock accuracy are specified by Byte 3 of the channel status. For additional information, refer to the IEC60958 standards. CS_DATA[27:24] , Sampling Frequency, HDMI Map, Address 0x39[3:0] Function CS_DATA[27:24] Description 0000 (default)

  • Page 81: Packets And Infoframes Registers

    Hardware User Guide UG-237 Channel Status Copyright Value Assertion It is possible to overwrite the copyright value of the channel status bit that is passed to the SPDIF output. This is done via the CS_COPYRIGHT_MANUAL and CS_COPYRIGHT_VALUE controls. CS_COPYRIGHT_MANUAL , Addr 68 (HDMI), Address 0x50[1] A control to select automatic or manual setting of the copyright value of the channel status bit that is passed to the SPDIF output.
  • Page 82 UG-237 Hardware User Guide InfoFrame Collection Mode The ADV7619 has two modes for storing the InfoFrame packet sent from the source into the internal memory. By default, the ADV7619 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame. The ADV7619 also provides a mode to store every InfoFrame sent from the source, regardless of a InfoFrame packet checksum error.
  • Page 83 Hardware User Guide UG-237 VS_INF_CKS_ERR_RAW , IO, Address 0x8D[0] (Read Only) Status of vendor specific InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an Vendor Specific InfoFrame. Once set, this bit will remain high until it is cleared via VS_INF_CKS_ERR_CLR. Function VS_INF_CKS_ERR_RAW Description...
  • Page 84 UG-237 Hardware User Guide Audio InfoFrame Registers Table 20 provides the list of readback registers available for the Audio InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the audio InfoFrame fields. Table 20. Audio InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 85 Hardware User Guide UG-237 SPD InfoFrame Registers Table 21 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 21. SPD InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 86 UG-237 Hardware User Guide MPEG Source InfoFrame Registers Table 22 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 22. MPEG InfoFrame Registers InfoFrame Map Address Access Type Register Name...
  • Page 87 Hardware User Guide UG-237 Vendor Specific InfoFrame Registers Table 23 provides a list of readback registers available for the vendor specific InfoFrame. Table 23. VS InfoFrame Registers InfoFrame Map Address Register Name Byte Name 0xEC VS_PACKET_ID[7:0] Packet type value 0xED VS_INF_VERS InfoFrame version number 0xEE...

  • Page 88: Packet Registers

    UG-237 Hardware User Guide PACKET REGISTERS ACP Packet Registers Table 24 provides the list of readback registers available for the ACP packets. Refer to the HDMI 1.3 specifications for a detailed explanation of the ACP packet fields. Table 24. ACP Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 89 Hardware User Guide UG-237 ISRC Packet Registers Table 25 and Table 26 provide lists of readback registers available for the ISRC packets. Refer to the HDMI 1.3 specifications for a detailed explanation of the ISRC packet fields. Table 25. ISRC1 Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 90 UG-237 Hardware User Guide The ISRC1 packet registers are considered valid if ISRC1_PCKT_RAW is set to 1. ISRC1_PCKT_RAW , IO, Address 0x60[6] (Read Only) Raw status signal of International Standard Recording Code 1 (ISRC1) packet detection signal. Function ISRC1_PCKT_RAW Description 0 (default) No ISRC1 packets received since the last HDMI packet detection reset.
  • Page 91 Hardware User Guide UG-237 Gamut Metadata Packets Refer to the HDMI specifications for a detailed explanation of the gamut metadata packet fields. Table 27. Gamut Metadata Packet Registers HDMI Map Address Register Name Packet Byte No. 0xF8 GAMUT_PACKET_ID[7:0] Packet type value 0xF9 GAMUT_HEADER1 0xFA...

  • Page 92: Customizing Packet/Infoframe Storage Registers

    UG-237 Hardware User Guide CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS The packet type value of each set of packet and InfoFrame registers in the InfoFrame map is programmable. This allows the user to configure the ADV7619 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port.

  • Page 93: Repeater Support

    Hardware User Guide UG-237 ISRC1_PACKET_ID[7:0] , Addr 7C (InfoFrame), Address 0xF2[7:0] ISRC1 InfoFrame ID. Function ISRC1_PACKET_ID[7:0] Description 0xxxxxxx Packet type value of packet stored in InfoFrame map, Address 0x8C to 0xA7 1xxxxxxx Packet type value of InfoFrame stored in InfoFrame map, Address 0x8C to 0xA7 ISRC2_PACKET_ID[7:0] , Addr 7C (InfoFrame), Address 0xF5[7:0] ISRC2 InfoFrame ID.
  • Page 94 UG-237 Hardware User Guide When KSV_LIST_READY is set to 1, the EDID/repeater controller computes the SHA-1 hash value V’ , updates the corresponding V’ registers (refer to Table 29), and sets the READY bit (that is, BCAPS[5]) to 1. This indicates to the transmitter attached to the ADV7619 that the KSV FIFO and SHA-1 hash value V’...
  • Page 95 Hardware User Guide UG-237 AKSV_UPDATE_A_RAW , IO, Address 0x88[0] (Read Only) Status of Port A AKSV update interrupt signal. When set to 1 it indicates that transmitter has written its AKSV into HDCP registers for Port A. Once set, this bit will remain high until it is cleared via AKSV_UPDATE_A_CLR. Function AKSV_UPDATE_A_RAW Description...
  • Page 96 UG-237 Hardware User Guide Function AKSV[39:0] Description 0x10[7:0] AKSV[7:0] 0x11[7:0] AKSV[15:8] 0x12[7:0] AKSV[23:16] 0x13[7:0] AKSV[31:24] 0x14[7:0] AKSV[39:32] BCAPS[7:0] , Addr 64 (Repeater), Address 0x40[7:0] This is the BCAPS register presented to the Tx attached to the active HDMI port. Function BCAPS[7:0] Description 10000011 (default)
  • Page 97 Hardware User Guide UG-237 KSV_MAP_SELECT[2:0] , Addr 64 (Repeater), Address 0x79[6:4] Selects which 128 bytes of KSV list will be accessed when reading or writing to addresses 0x80 to 0xFF in this map. Values from 5 and upwards are not valid Function KSV_MAP_SELECT[2:0] Description...
  • Page 98 UG-237 Hardware User Guide KSV Byte Number Register Name Register Addresses KSV_BYTE_38[7:0] 0xA6[7:0] KSV_BYTE_39[7:0] 0xA7[7:0] KSV_BYTE_40[7:0] 0xA8[7:0] KSV_BYTE_41[7:0] 0xA9[7:0] KSV_BYTE_42[7:0] 0xAA[7:0] KSV_BYTE_43[7:0] 0xAB[7:0] KSV_BYTE_44[7:0] 0xAC[7:0] KSV_BYTE_45[7:0] 0xAD[7:0] KSV_BYTE_46[7:0] 0xAE[7:0] KSV_BYTE_47[7:0] 0xAF[7:0] KSV_BYTE_48[7:0] 0xB0[7:0] KSV_BYTE_49[7:0] 0xB1[7:0] KSV_BYTE_50[7:0] 0xB2[7:0] KSV_BYTE_51[7:0] 0xB3[7:0] KSV_BYTE_52[7:0] 0xB4[7:0] KSV_BYTE_53[7:0] 0xB5[7:0]...
  • Page 99 Hardware User Guide UG-237 KSV Byte Number Register Name Register Addresses KSV_BYTE_91[7:0] 0xDB[7:0] KSV_BYTE_92[7:0] 0xDC[7:0] KSV_BYTE_93[7:0] 0xDD[7:0] KSV_BYTE_94[7:0] 0xDE[7:0] KSV_BYTE_95[7:0] 0xDF[7:0] KSV_BYTE_96[7:0] 0xE0[7:0] KSV_BYTE_97[7:0] 0xE1[7:0] KSV_BYTE_98[7:0] 0xE2[7:0] KSV_BYTE_99[7:0] 0xE3[7:0] KSV_BYTE_100[7:0] 0xE4[7:0] KSV_BYTE_101[7:0] 0xE5[7:0] KSV_BYTE_102[7:0] 0xE6[7:0] KSV_BYTE_103[7:0] 0xE7[7:0] KSV_BYTE_104[7:0] 0xE8[7:0] KSV_BYTE_105[7:0] 0xE9[7:0] KSV_BYTE_106[7:0] 0xEA[7:0]...

  • Page 100: Interface To Dpp Section

    UG-237 Hardware User Guide Register Name Address Location Function SHA_D[31:0] 0x2C[7:0]: SHA_D[7:0] H3 part of SHA-1 hash value V’ . Register also called (V’ . H3) 0x2D[7:0]: SHA_D[15:8] 0x2E[7:0]: SHA_D[23:16] 0x2F[7:0]: SHA_D[31:24] SHA_E[31:0] 0x30[7:0]: SHA_E[7:0] H4 part of SHA-1 hash value V’ . Register also called (V’ . H4) 0x31[7:0]: SHA_E[15:8] 0x32[7:0]: SHA_E[23:16] 0x33[7:0]: SHA_E[31:24]...

  • Page 101: Pass Through Mode

    Hardware User Guide UG-237 UP_CONVERSION_MODE , Addr 68 (HDMI), Address 0x1D[5] A control to select linear or interpolated 4:2:2 to 4:4:4 conversion. A 4:2:2 incoming stream is upconverted to a 4:4:4 stream before being sent to the CP. Function UP_CONVERSION_MODE Description 0 (default) Cr and Cb samples are repeated in their respective channel...

  • Page 102: Color Space Information Sent To The Dpp And Cp Sections

    UG-237 Hardware User Guide DPP_BYPASS_EN , Addr 44 (CP), Address 0xBD[4] Manual control to enable DPP block. Function DPP_BYPASS_EN Description 1 (default) DPP bypassed DPP enabled COLOR SPACE INFORMATION SENT TO THE DPP AND CP SECTIONS The HDMI section sends information regarding the color space of the video it outputs to the DPP and the CP sections. This color space information is derived from the DVI/HDMI status of the input stream the HDMI stection processes and from the AVI InfoFrame that the HDMI section decodes from the input stream.
  • Page 103 Hardware User Guide UG-237 Table 31. HDMI Flags in IO Map Register 0x65 Bit Name Bit Position Description GAMUT_MDATA_RAW 0 (LSB) Returns 1 if a Gamut Metadata packet was received. For additional information, see the Gamut Metadata Packets section. AUDIO_C_PCKT_RAW Returns 1 if an audio clock regeneration packet has been received.
  • Page 104 UG-237 Hardware User Guide Table 35. HDMI Flags in IO Map Register 0x7E Bit Name Bit Position Description NEW_GAMUT_MDATA_RAW 0 (LSB) When set to 1 indicates that a gamut metadata packet with new content has been received. Once set, this bit remains high until the interrupt is cleared via NEW_GAMUT_ MDATA_PCKT_CLR.

  • Page 105: Hdmi Section Reset Strategy

    Hardware User Guide UG-237 Table 37. HDMI InfoFrame Checksum Error Flags in IO Map Bit Name IO Map Location Description AVI_INF_CKS_ERR_RAW 0x88[4] Description available in the InfoFrame Checksum Error Flags section AUD_INF_CKS_ERR_RAW 0x88[5] Description available in the InfoFrame Checksum Error Flags section SPD_INF_CKS_ERR_RAW 0x88[6] Description available in the InfoFrame Checksum Error Flags section...

  • Page 106: Data Preprocessor And Color Space Conversion And Color Controls

    UG-237 Hardware User Guide DATA PREPROCESSOR AND COLOR SPACE CONVERSION AND COLOR CONTROLS COLOR SPACE CONVERSION MATRIX The ADV7619 provides any-to-any color space support. It supports formats such as RGB, YUV, YCbCr and many other color spaces. Data Preprocessor and Component Processor are designed to run at speeds of up to 170 MHz. Therefore HDMI video with pixel clock frequencies above 170 MHz must be routed directly to Video Output Formatter bypassing Data Preprocessor (DPP) and Component Preprocessor (CP).
  • Page 107 Hardware User Guide UG-237 Selecting Auto or Manual CP CSC Conversion Mode The ADV7619 CP CSC provides two modes for the CSC configuration: automatic CSC mode and manual CSC mode. In automatic CSC mode, the user is required to program the input color space and the output color space for the correct operation of the CSC matrix.
  • Page 108 UG-237 Hardware User Guide RGB_OUT , IO, Address 0x02[1] A control to select output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. It is used in conjunction with the INP_COLOR_SPACE[3:0] and ALT_GAMMA bits to select the applied CSC. Function RGB_OUT Description...
  • Page 109 Hardware User Guide UG-237 HDMI Automatic CSC Operation In HDMI mode, the ADV7619 provides an automatic CSC function based on the AVI InfoFrame sent from the source. The flowchart in Figure 34 shows the mechanism of the ADV7619 auto CSC functionality in HDMI mode. Note: In the following flowcharts, a red dashed line represents a state that is undefined according to the CEA-861D specification, and therefore should never happen.
  • Page 110 UG-237 Hardware User Guide Y[1:0] = 01b, 10b, 11b YCbCr MODE START YCbCr COLORIMETRY C[1:0] = xxb? C[1:0] = 10b C[1:0] = 10b C[1:0] = 00b C[1:0] = 11b YUV709 YUV601 EXTENDED COLORIMETRY EC[2:0] = xxxb? EC[2:0] = 001b EC[2:0] = 000b EC[2:0] != (001 OR 000) xvYCC709 xvYCC601...
  • Page 111 Hardware User Guide UG-237 Y[1:0] = 00b RGB 4:4:4 MODE START DETECT QUANTIZATION RANGE Q[1:0] = xxb? Q[1:0] = 01b Q[1:0] = 00b Q[1:0] = 10b QZERO_RGB_FULL = 0 QZERO_RGB_FULL = 1 (DEFAULT) 1-BIT CONTROL TO SELECT FULL/LIMITED RGB/RANGE RGB LIMITED RANGE RGB FULL RANGE Figure 38.
  • Page 112 UG-237 Hardware User Guide CSC_SCALE A1[12:0] A4[12:0] ×2 OUT_A[11:0] IN_A[11:0] × A2[12:0] IN_B[11:0] × A3[12:0] IN_C[11:0] × Figure 39. Single CSC Channel The coefficients mentioned previously are detailed in Table 43 along with the default values for these coefficients. Table 43. CSC Coefficients Function Bit CP Map Address Reset Value (Hex)
  • Page 113 Hardware User Guide UG-237 CSC Manual Programming The equations performed by the CP CSC are as follows: CSC Channel A ⎡ ⎤ × × × × scale ⎢ ⎣ ⎥ ⎦ 4096 4096 4096 CSC Channel B ⎡ ⎤ × ×...

  • Page 114: Changes To Check The Value Of Each Coefficient Section

    UG-237 Hardware User Guide The ranges of the three equations are shown in Table 44. Table 44. Equation Ranges Equation Minimum Value Maximum Value Range 0 + 0 + 0 = 0 0.59 + 0.3 + 0.11 = 1 [0 … 1] = 1 (−0.34) + (−0.17) = −0.51 0.51 [−0.51 …+ 0.51] = 1.02...

  • Page 115: Color Controls

    Hardware User Guide UG-237 CSC in Pass-Through Mode It is possible to configure the CP CSC in a pass-through mode. In this mode, the CP CSC is used but does not alter the data it processes. The CP CSC pass-through mode is obtained using the following settings: Set MAN_CP_CSC_EN to 1’b1.

  • Page 116: Changes To Cp_Hue[7:0], Addr 44 (Cp), Address 0X3D[7:0] Section

    UG-237 Hardware User Guide CP_BRIGHTNESS[7:0], Addr 44 (CP), Address 0x3C[7:0] A control to set the brightness. This field is a signed value. The effective brightness value applied to the luma is obtained by multiplying the programmed value CP_BRIGHTNESS with a gain of 4. The brightness applied to the luma has a range of [−512 to +508]. This control is functional if VID_ADJ_EN is set to 1.

  • Page 117: Component Processor

    Hardware User Guide UG-237 COMPONENT PROCESSOR COMPONENT PROCESSING STANDARD SYNC PROCESSING IDENTIFICATION CHANNEL (STDI) HS/VS/F SYNC EXTRACTOR OUTPUT VIDEO DATA CHA, CHB, AND CHC OUTPUT MEASUREMENT DIGITAL VIDEO DATA BLOCK (≥I GAIN OFFSET AV CODE DELAY FINE CHA, CHB, AND CP CSC CONTROL ADDER...
  • Page 118 UG-237 Hardware User Guide Note: The target clamp level for black input is a digital code of 0. This is to facilitate the highest possible signal to noise ratio (SNR). Some interfaces, for example, ITU-R. BT656, require black to correspond to a value other than 0. To facilitate this, there is an additional independent offset adder block after the gain multipliers for which separate fixed offset values can be supplied.

  • Page 119: Cp Gain Operation

    Hardware User Guide UG-237 CLMP_C[11:0] , Addr 44 (CP), Address 0x6F[3:0]; Address 0x70[7:0] Manual clamp value for Channel C. This field is an unsigned 12-bit value to be subtracted from the incoming video signal. This value programmed in this register is effective if the CLMP_BC_MAN is set to 1. To change the CLMP_C[11:0], Register Address 0x6F and Register Address 0x70 must be updated with the desired clamp value written to in this order and with no other I C access in between.
  • Page 120 UG-237 Hardware User Guide AGC_MODE_MAN GAIN_MAN HDMI_MODE SSPD DETECTED EMBEDDED SYNCS?? INPUT GAIN GAIN OP_656_RANGE OP_656_RANGE SET GAIN BASED ON RANGE A/B/C_GAIN[9:0] VALUE (255 – 0 + 1) × 0 (0 TO 255 OUTPUT) 0 (0 TO 255 OUTPUT) 16/1344 = 3.047 0 TO 255 1 (16 TO 235 Y/RGB (235 –...
  • Page 121 Hardware User Guide UG-237 A_GAIN[9:0] , Addr 44 (CP), Address 0x73[5:0]; Address 0x74[7:4] A control to set the manual gain value for Channel A. This register is an unsigned value in a 2.8 binary format. To change A_GAIN[9:0], the register at Address 0x73 and Address 0x74 must be written to in this order with no I C access in between.

  • Page 122: Cp Offset Block

    UG-237 Hardware User Guide Function CP_GAIN_FILT[3:0] Description 0000 (default) No filtering, that is, coefficient A = 1. 0001 Coefficient A = 1/128 lines. 0010 Coefficient A = 1/256 lines. 0011 Coefficient A = 1/512 lines. 0100 Coefficient A = 1/1024 lines. 0101 Coefficient A = 1/2048 lines.
  • Page 123 Hardware User Guide UG-237 C REGISTER VALUE OFFSET_A/B/C[9:0] == 0x3FF USE VALUE FROM I C REGISTER OFFSET_A/B/C[9:0] DIRECTLY OFFSET CHANNEL RGB_OUT = 1 RGB_OUT = 0 OP_656_RANGE = 1 OP_656_RANGE = 0 OP_656_RANGE = 1 OP_656_RANGE = 0 64dec 0dec 64dec 0dec 64dec...

  • Page 124: Av Code Block

    UG-237 Hardware User Guide C_OFFSET[9:0] , Addr 44 (CP), Address 0x79[1:0]; Address 0x7A[7:0] A control to set the manual offset for Channel C. This field stores an unsigned value. To change C_OFFSET[9:0], Register Address 0x79 and Register Address 0x7A must be written to in this order with no I C access in between.

  • Page 125: Cp Data Path For Hdmi Modes

    Hardware User Guide UG-237 AV_INV_F , Addr 44 (CP), Address 0x7B[7] A control to invert the F bit in the AV codes. Function AV_INV_F Description 0 (default) Inserts the F bit with default polarity Inverts the F bit before inserting it into the AV code DATA_BLANK_EN , IO, Address 0x05[3] A control to blank data during video blanking sections.
  • Page 126 UG-237 Hardware User Guide Table 49. Settings Required to Support Extended Range Video Input C Setting/Mode Analog Modes HDMI Mode YUV HDMI Mode RGB [0 to 255] HDMI Mode RGB [16 to 235] OP_656_RANGE ALT_DATA_SAT Pregain Block To compensate for signal attenuation in the analog front end of the ADV7619 and input buffer gain, a pregain block is provided in the CP path.
  • Page 127 Hardware User Guide UG-237 HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLMP_A[11:0] CLAMP RGB_OUT 12-BIT CLMP_A_MAN 12'd0 HDMI_CLMP_ENABLE AUTO VALUE 12'd2056 (16 @ 8-BIT) AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN A_GAIN[9:0] CP_OP_656_SEL* × × 10'd220 (×0.86) GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)
  • Page 128 UG-237 Hardware User Guide HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLMP_B[11:0]/CLMP_C[11:0] CLAMP RGB_OUT 12-BIT CLMP_BC_MAN 12'd0 HDMI_CLMP_ENABLE 12'd2048 (128 @ 8-BIT) AUTO VALUE AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN B_GAIN[9:0]/C_GAIN[9:0] CP_OP_656_SEL* 10'd220 (×0.86) × × GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)

  • Page 129: Sync Processed By Cp Section

    Hardware User Guide UG-237 SYNC PROCESSED BY CP SECTION The CP Core uses the HDMI section as its source of HSync, VSync and DE. Sync Routing from HDMI Section The CP section receives syncs from the HDMI section, as shown in Figure 46. PRIM_MODE[2] HS 1 HDMI HS...
  • Page 130 UG-237 Hardware User Guide In ADV7619, there are three operational modes for the STDI block: • Continuous mode: The STDI block performs continuous measurements on lock/unlock bases and updates the corresponding I C registers based on the lock status bit (STDI_DVALID). •...
  • Page 131 Hardware User Guide UG-237 CH1_STDI_DVALID , Addr 44 (CP), Address 0xB1[7] (Read Only) This bit is set when the measurements performed by Sync Channel 1 STDI are completed. High level signals validity for CH1_BL, CH1_LCF, CH1_LCVS, CH1_FCL, and CH1_STDI_INTLCD parameters. To prevent false readouts, especially during signal acquisition, CH1_SDTI_DVALID only goes high after four fields with same length are recorded.
  • Page 132 UG-237 Hardware User Guide Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism STDI Horizontal Locking Operation For the STDI horizontal locking operation, the STDI block compares adjacent line length differences (in XTAL clock cycles) with the programmed threshold. If 128 consecutive adjacent lines lengths are within the threshold, the STDI horizontally locks to the incoming video.
  • Page 133 Hardware User Guide UG-237 FIELD2 – FIELD3 ≤ THRESHOLD? FIELD4 – FIELD5 ≤ THRESHOLD? FIELD1 – FIELD2 ≤ THRESHOLD? FIELD3 – FIELD4 ≤ THRESHOLD? FIELD 1 FIELD 2 FIELD 3 FIELD 4 FIELD 5 FIELD 6 ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO...
  • Page 134 UG-237 Hardware User Guide CH1_FCL[12:0] , Addr 44 (CP), Address 0xB8[4:0]; Address 0xB9[7:0] (Read Only) A readback for the Sync Channel 1 field count length. Number of crystal clock cycles between successive VSyncs measured by Sync Channel 1 STDI or in 1/256th of a field. The readback from this field is valid if CH1_STDI_DVALID is high.
  • Page 135 Hardware User Guide UG-237 STDI Readback Values Table 50. STDI Readback Values for SD, PR, and HD Standard CHx_BL[13:0] 28.63636 MHz XTAL CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0] 28.63636 MHz XTAL 720p SMPTE 296M 5091 4 to 5 1868 1125i SMPTE 274M 6788 562 to 563 4 to 5 1868...

  • Page 136: Cp Output Synchronization Signal Positioning

    UG-237 Hardware User Guide 1200 1000 VGA 72 VGA 75 2000 4000 6000 8000 28.6363MHz SAMPLES IN 8-LINE BLOCK Figure 52. STDI Values for GR Mode (Plot) Note: Although the two points for VGA72 and VGA75 look very close, it is anticipated that the difference in the parameters is sufficient to distinguish between them.
  • Page 137 Hardware User Guide UG-237 As shown in Figure 53, the ADV7619 CP can output the following three primary and one secondary synchronization signals, which are controlled by the output control block in the CP block. Primary: • Horizontal synchronization timing reference output on the HS pin •...
  • Page 138 UG-237 Hardware User Guide CP Synchronization Signals The three primary synchronization signals have certain default positions, depending on the video standard in use. To allow for a glueless interface to downstream ICs, there is the facility to adjust the position of edges on the three primary synchronization signals Figure 55, Figure 56, Figure 57, Figure 58, Figure 59, Figure 60, Figure 61, Figure 62, show the nominal position of HS, VS, and FIELD.
  • Page 139 Hardware User Guide UG-237 PIXEL BUS ..... H BLANK ACTIVE VIDEO ACTIVE VIDEO HS OUTPUT START_HS[9:0] END_HS[9:0] 4 LLC1 Figure 55. HS Timing START_HS[9:0] , Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0] A control to shift the position of the leading edge of the HSync output by the CP core. This register stores a signed value in a twos complement format.
  • Page 140 UG-237 Hardware User Guide END_HS[9:0], Addr 44 (CP), Address 0x7C[1:0]; Address 0x7D[7:0] A control to shift the position of the trailing edge of the HSync output by the CP core. This register stores a signed value in a twos complement format. HS_END[9:0] is the number of pixel clocks by which the leading edge of the HSync is shifted (for example, 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks toward the active video).
  • Page 141 Hardware User Guide UG-237 Function START_VS[3:0] Description 0x0 (default) Default value. 0x0 to 0x7 The leading edge of the VSync is shifted toward the active video. 0x8 to 0xF The leading edge of the VSync is shifted away from the active video. Table 60.
  • Page 142 UG-237 Hardware User Guide END_VS_EVEN[3:0] , Addr 44 (CP), Address 0x89[3:0] A control to shift the position of the trailing edge of the Vsync output by the CP core. This register stores a signed value in a twos complement format. SEND_VS_EVEN[3:0] is the number of lines by which the trailing edge of the Vsync is shifted (for example, 0x0F corresponds to a shift of 1 line toward the active video, 0x01 corresponds to a shift of 1 line away from the active video).
  • Page 143 Hardware User Guide UG-237 DE_V_END[3:0] , Addr 44 (CP), Address 0x8E[3:0] A control to vary the position of the end of the VBI region. This register stores a signed value represented in a twos complement format. The unit of DE_V_START[9:0] is one line. Function DE_V_END[3:0] Description...
  • Page 144 UG-237 Hardware User Guide Table 63. Controlling the Even Field Section of the FIELD Timing Signal START_FE[3:0] Result Note 0000 (default) No move (default) Minimum → 0001 1 HS shift later than default 0011 3 HS shift later than default Maximum →...
  • Page 145 Hardware User Guide UG-237 FIELD 1 15… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 2 6 2 277… OUTPUT VIDEO HS OUTPUT VS OUTPUT END_VS[3:0] START_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 56. 525i VS Timing Rev.
  • Page 146 UG-237 Hardware User Guide FIELD 1 11… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 323… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 57. 625i VS Timing OUTPUT VIDEO OUTPUT END_VS[3:0] OUTPUT START_VS[3:0]...
  • Page 147 Hardware User Guide UG-237 OUTPUT VIDEO 8… OUTPUT OUTPUT END_VS[3:0] START_VS[3:0] Figure 60. 720p VS Timing FIELD 1 OUTPUT VIDEO 1123 1124 1125 8… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 OUTPUT VIDEO 5 6 3 570… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0]...

  • Page 148: Cp Hdmi Controls

    UG-237 Hardware User Guide CP HDMI CONTROLS HDMI_CP_LOCK_THRESHOLD[1:0] , Addr 44 (CP), Address 0xCB[1:0] Locking time of filter used for buffering of timing parameters in HDMI mode. Function HDMI_CP_LOCK_THRESHOLD[1:0] Description 00 (default) Slowest locking time Medium locking time Fastest locking time Fixed step size of 0.5 pixels FREE RUN MODE Free run mode provides the user with a stable clock and predictable data if the input signal cannot be decoded, for example, if input video...
  • Page 149 Hardware User Guide UG-237 Notes • This parameter has no effect on the video decoding. • If CH1_FR_LL[10:0] is not programmed, then the free-run line length parameter is decoded from PRIM_MODE[3:0] and VID_STD[5:0]. Vertical Conditions In the case of the vertical conditions, the STDI section measures the number of lines per field of incoming video signal. This value is compared with an internally stored vertical parameter, the ideal field length.
  • Page 150 UG-237 Hardware User Guide Notes • The CP_LCOUNT_MAX[11:0] parameter has no effect on the video decoding. • If CP_LCOUNT_MAX[11:0] is not programmed, then the Free-run Line Length parameter is decoded from PRIM_MODE[3:0] and VID_STD[5:0] . • If CP_LCOUNT_MAX[11:0] is programmed, then Free-run Line Length parameter defined by CP_LCOUNT_MAX[11:0] and INTERLACED, is used for Channel 1.
  • Page 151 Hardware User Guide UG-237 Free Run Default Color Output In the event of loss of input signal, the ADV7619 may enter free run and can be configured to output a default color rather than noise. The default color values are given in Table 65. The times at which the default colors are inserted can be set as follows: •...

  • Page 152: Cp Status

    UG-237 Hardware User Guide DEF_COL_CHB[7:0] , Addr 44 (CP), Address 0xC1[7:0] A control to set the default color for Channel B. To be used if CP_DEF_COL_MAN_VAL is 1. Function DEF_COL_CHB[7:0] Description 0x00 (default) Default value DEF_COL_CHC[7:0] , Addr 44 (CP), Address 0xC2[7:0] A control to set the default color for Channel C.

  • Page 153: Consumer Electronics Control

    Hardware User Guide UG-237 CONSUMER ELECTRONICS CONTROL The Consumer Electronics Control (CEC) module features the hardware required to behave as an initiator or a follower as per the specifications for a CEC device. The CEC module contains four main sections: •...

  • Page 154: Cec Transmit Section

    UG-237 Hardware User Guide CEC TRANSMIT SECTION The transmit section features the hardware required for the CEC module to act as an initiator. The host utilizes this section to transmit directly addressed messages or broadcast messages on the CEC bus. When the host wants to a send message to other CEC devices, it writes the message to the CEC outgoing message registers (refer to Table 66) and the message length register.
  • Page 155 Hardware User Guide UG-237 CEC_TX_READY_ST , IO, Address 0x93[0] (Read Only) Latched status of CEC_TX_READY_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When the CEC TX successfully sends the current message this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_TX_READY_CLR.

  • Page 156: Cec Receive Section

    UG-237 Hardware User Guide CEC RECEIVE SECTION The receive section features the hardware required for the CEC module to act as a follower. Once the CEC module is powered up via the CEC_POWER_UP bit the CEC Rx section will immediately begin monitoring the CEC bus for messages with the correct logical address(es).
  • Page 157 Hardware User Guide UG-237 Receive Buffers The ADV7619 features three frame buffers that allow the receiver to receive up to three messages before the host processor needs to read a message out. When three messages have been received, no further message reception is possible until the host reads at least one message.
  • Page 158 UG-237 Hardware User Guide CEC_RX_RDY0_ST , IO, Address 0x93[3] (Read Only) Latched status of CEC_RX_RDY0_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When a message has been received into Buffer 0, this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_RX_RDY0_CLR.
  • Page 159 Hardware User Guide UG-237 CEC_BUF0_RX_FRAME_LENGTH[4:0] , Addr 80 (CEC), Address 0x25[4:0] (Read Only) Function CEC_BUF0_RX_FRAME_LENGTH[4:0] Description xxxxx The total number of bytes (including header byte) that were received into Buffer 0 CEC_CLR_RX_RDY0 , Addr 80 (CEC), Address 0x2C[1] (Self-Clearing) Clear control for CEC_RX_RDY0. Function CEC_CLR_RX_RDY0 Description...
  • Page 160 UG-237 Hardware User Guide Table 69. CEC Incoming Frame Buffer 2 Registers Register Name CEC Map Address Description CEC_BUF2_RX_FRAME_HEADER[7:0] 0x65 Header of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA0[7:0] 0x66 Byte 0 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA1[7:0] 0x67 Byte 1 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA2[7:0] 0x68 Byte 2 of message in Frame Buffer 2...

  • Page 161: Antiglitch Filter Module

    Hardware User Guide UG-237 Another message is received. The receiver module checks to see which of the three buffers are available, starting with Buffer 0. In this example, Buffer 0 has been read out already by the host processor and is available so the new message is stored in Receive Buffer 0. At this time the timestamp for Receive Buffer 1 is adjusted to 0b01 to show that it contains the first received message, and a timestamp of 0b10 is assigned to Receive Buffer 0 to show that it contains the second received message.

  • Page 162: Typical Operation Flow

    UG-237 Hardware User Guide TYPICAL OPERATION FLOW This section describes the algorithm that should be implemented in the host processor controlling the CEC module. Initializing CEC Module Figure 65 shows the flow that can be implemented in the host processor controlling the ADV7619 to initialize the CEC module. START SET CEC_POWER_UP TO 1 ENABLE...
  • Page 163 Hardware User Guide UG-237 Using CEC Module as Initiator Figure 66 shows the algorithm that can be implemented in the host processor controlling the ADV7619 to use the CEC module as an initiator. START WRITE THE OUTGOING CEC COMMAND INTO THE OUTGOING MESSAGE REGISTERS (CEC MAP REG 0x00 TO 0x0F) SET CEC_TX_FRAME_LENGTH...
  • Page 164 UG-237 Hardware User Guide Using CEC Module as Follower Figure 67 shows the algorithm that can be implemented in the host processor controlling the ADV7619 to use the CEC module as a follower. START (WAIT FOR INTERRUPT) CEC_RX_RDY0_ST CEC_RX_RDY1_ST CEC_RX_RDY2_ST = 1? = 1? = 1?

  • Page 165: Low Power Cec Message Monitoring

    Hardware User Guide UG-237 LOW POWER CEC MESSAGE MONITORING The ADV7619 can be programmed to monitor the CEC line for messages that contain specific, user-programable opcodes. These are referred to as “WAKE_OPCODEs” as they allow the system to go into a low power or sleep mode and be woken up when an opcode of interest is received, without the host processor having to check each received message.
  • Page 166 UG-237 Hardware User Guide CEC_WAKE_OPCODE4[7:0] , Addr 80 (CEC), Address 0x7C[7:0] CEC_WAKE_OPCODE4 This value can be set to a CEC opcode that requires a response. On receipt of this opcode the Rx generates an interrupt that can be used to alert the system that a CEC opcode of interest has been received and requires a response. Function CEC_WAKE_OPCODE4[7:0] Description...

  • Page 167: Interrupts

    Hardware User Guide UG-237 INTERRUPTS INTERRUPT ARCHITECTURE OVERVIEW The ADV7619 interrupt architecture provides four different types of bits, namely • Raw bits • Status bits • Interrupt mask bits • Clear bits Raw bits are defined as being either edge-sensitive or level-sensitive. The following example compares AVI_INFO_RAW and NEW_AVI_INFO_RAW to demonstrate the difference.
  • Page 168 UG-237 Hardware User Guide AVI_INFO_ST , IO, Address 0x61[0] (Read Only) Latched status of AVI_INFO_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Once set, this bit will remain high until the interrupt is cleared via AVI_INFO_CLR. Function AVI_INFO_ST Description...
  • Page 169 Hardware User Guide UG-237 NEW_AVI_INFO_MB2 , IO, Address 0x7C[0] INT2 interrupt mask for new AVI InfoFrame detection interrupt. When set a new AVI InfoFrame detection event will cause NEW_AVI_INFO_ST to be set and an interrupt will be generated on INT2. Function NEW_AVI_INFO_MB2 Description...

  • Page 170: Interrupt Pins

    UG-237 Hardware User Guide NEW AVI INFOFRAME DETECTION INTERNAL PULSE FLAG AVI INFOFRAME WITH NEW CONTENT DETECT TIME > 2XTAL PERIODS NEW_AVI_INFO_RAW NEW_AVI_INFO_ST NEW_AVI_INFO_CLR SET TO 1 TIME TAKEN BY THE CPU TO CLEAR NEW_AVI_INFO_ST Figure 70. NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing In this section, all raw bits are classified as being triggered by either level sensitive or edge sensitive events, with the following understanding of the terminology •...

  • Page 171: Changes To Int2_Pol, Io, Address 0X41[2] Section

    Hardware User Guide UG-237 Interrupt Duration The interrupt duration can be programmed independently for INT1 and INT2. When an interrupt event occurs, the interrupt pin INT1 or INT2 becomes active with a programmable duration as described below. INTRQ_DUR_SEL[1:0] , IO, Address 0x40[7:6] A control to select the interrupt signal duration for the interrupt signal on INT1.
  • Page 172 UG-237 Hardware User Guide MPU_STIM_INTRQ_MB1 , IO, Address 0x4B[7] INT1 interrupt mask for manual forced interrupt signal. When set the manual forced interrupt will trigger the INT1 interrupt and MPU_STIM_INTRQ_ST will indicate the interrupt status. Function MPU_STIM_INTRQ_MB1 Description 0 (default) Disables manual forced interrupt for INT1 Enables manual forced interrupt for INT1 MPU_STIM_INTRQ_MB2 , IO, Address 0x4A[7]...

  • Page 173: Description Of Interrupt Bits

    Hardware User Guide UG-237 DESCRIPTION OF INTERRUPT BITS This section lists all the raw bits in the IO map of the ADV7619 by category, and states whether the bit is an edge or level sensitive bit. A basic explanation for each bit is provided in the software manual and/or in the corresponding section of the hardware manual. For certain interrupts that require additional explanations, these are provided in the Additional Explanations section.

  • Page 174: Additional Explanations

    UG-237 Hardware User Guide • HDMI_ENCRPT_B_RAW • CABLE_DET_A_RAW • CABLE_DET_B_RAW • V_LOCKED_RAW • DE_REGEN_LCK_RAW • VIDEO_3D_RAW • RI_EXPIRED_A_RAW • RI_EXPIRED_B_RAW The following raw bits are all related to HDMI operation and are based on edge sensitive events; it is, therefore, necessary to clear these bits using the corresponding clear bit.
  • Page 175 Hardware User Guide UG-237 Function STDI_DATA_VALID_EDGE_SEL Description Generate interrupt for a low to high change in STDI_VALID status 1 (default) Generate interrupt for a low to high or a high to low change in STDI_VALID status CP_LOCK, CP_UNLOCK CP_UNLOCK_RAW is programmable as either an edge sensitive bit or a level sensitive bit using the following control. Note that this control also configures whether an interrupt is generated only on the rising edge of CP_UNLOCK_RAW, or on both edges.
  • Page 176 UG-237 Hardware User Guide Group 3 HDMI Interrupts The interrupts listed in Table 73 are valid under the following conditions: • ADV7619 is configured in HMDI mode • TMDS_CLK_A_RAW is set to 1 if Port A is the active HDMI port •...
  • Page 177 Hardware User Guide UG-237 Storing Masked Interrupts STORE_UNMASKED_IRQS , IO, Address 0x40[4] STORE_MASKED_IRQS allows the HDMI status flags for any HDMI interrupt to be triggered regardless of whether the mask bits are set. This bit allows a HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without triggering an interrupt on the interrupt pin.
  • Page 178 UG-237 Hardware User Guide INTERRUPT_STATUS_6 register consists of fields: CP_LOCK_CH1_ST, CP_UNLOCK_CH1_ST, and STDI_DVALID_CH1_ST. CP_LOCK_CH1_ST , IO, Address 0x5C[3] (Read Only) Function CP_LOCK_CH1_ST Description 0 (default) No change. An interrupt has not been generated from this register. Channel 1 CP input has caused the decoder to go from an unlocked state to a locked state. CP_UNLOCK_CH1_ST , IO, Address 0x5C[2] (Read Only) Function CP_UNLOCK_CH1_ST...
  • Page 179 Hardware User Guide UG-237 VS_INFO_ST , IO, Address 0x61[4] (Read Only) Latched status of vendor specific InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via VS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function VS_INFO_ST Description...
  • Page 180 UG-237 Hardware User Guide AV_MUTE_ST , IO, Address 0x66[5] (Read Only) Latched status of AV mute detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via AV_MUTE_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function AV_MUTE_ST Description...
  • Page 181 Hardware User Guide UG-237 CABLE_DET_B_ST , IO, Address 0x6B[7] (Read Only) Latched status of Port B +5 V cable detection interrupt signal. Once set, this bit remains high until the interrupt has been cleared via CABLE_DET_B_CLR. This bit is only valid if enabled via corresponding the INT1 or INT2 interrupt mask bit. Function CABLE_DET_B_ST Description...
  • Page 182 UG-237 Hardware User Guide V_LOCKED_ST , IO, Address 0x6B[1] (Read Only) Latched status for the vertical sync filter locked interrupt. Once set, this bit will remain high until the interrupt is cleared via V_LOCKED_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function V_LOCKED_ST Description...
  • Page 183 Hardware User Guide UG-237 NEW_ISRC1_PCKT_ST , IO, Address 0x7A[6] (Read Only) Latched status for the new ISRC1 packet interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_ISRC1_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function NEW_ISRC1_PCKT_ST Description...
  • Page 184 UG-237 Hardware User Guide FIFO_NEAR_OVFL_ST , IO, Address 0x7F[7] (Read Only) Latched status for the audio FIFO near overflow interrupt. Once set, this bit will remain high until the interrupt is cleared via FIFO_OVFL_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function FIFO_NEAR_OVFL_ST Description...
  • Page 185 Hardware User Guide UG-237 AUDIO_PCKT_ERR_ST , IO, Address 0x7F[1] (Read Only) Latched status for the audio packet error interrupt. Once set, this bit will remain high until the interrupt is cleared via AUDIO_PCKT_ERR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function AUDIO_PCKT_ERR_ST Description...
  • Page 186 UG-237 Hardware User Guide NEW_SAMP_RT_ST , IO, Address 0x84[3] (Read Only) Latched status of new sampling rate interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_SAMP_RT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function NEW_SAMP_RT_ST Description...
  • Page 187 Hardware User Guide UG-237 Function AUD_INF_CKS_ERR_ST Description 0 (default) No change in audio InfoFrame checksum error An audio InfoFrame checksum error has triggered this interrupt AVI_INF_CKS_ERR_ST , IO, Address 0x89[4] (Read Only) Latched status of AVI InfoFrame checksum error interrupt. Once set, this bit will remain high until the interrupt is cleared via AVI_INF_CKS_ERR_CLR.
  • Page 188 UG-237 Hardware User Guide BG_MEAS_DONE_ST, IO, Address 0x8E[1] (Read Only) Latched status of background port measurement completed interrupt. Once set, this bit will remain high until the interrupt has been cleared via BG_MEAS_DONE_CLR. This bit is only valid if enabled via corresponding the INT1 or INT2 interrupt mask bit. Function BG_MEAS_DONE_ST Description...

  • Page 189: Register Access And Serial Ports Description

    Hardware User Guide UG-237 REGISTER ACCESS AND SERIAL PORTS DESCRIPTION The ADV7619 has three 2-wire serial (I C compatible) ports: • One main I C port, SDA/SCL, allows a system I C master controller to control and configure the ADV7619 •...
  • Page 190 UG-237 Hardware User Guide write command to IO 0x1B, SAMPLE_ALSB, one part (with VS/FIELD/ALSB left floating) will get Address 0x98 and the second part (with VS/FIELD/ALSB pulled high) will have an address of 0x9A. SAMPLE_ALSB , IO, Address 0x1B[0] When HIGH, VS/FIELD/ALSB pin is sampled to be used as ALSB value for IO map. Function SAMPLE_ALSB Description...

  • Page 191: Ddc Ports

    Hardware User Guide UG-237 DPLL_SLAVE_ADDR[6:0] , IO, Address 0xF8[7:1] Programmable I C slave address for DPLL map Function DPLL_SLAVE_ADDR[6:0] Description 0x00 (default) Map not accessible 0xXX DPLL Map Slave address Protocol for Main I C Port The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains high.
  • Page 192 UG-237 Hardware User Guide C Protocols for Access to the Internal EDID An I C master connected on a DDC port can access the internal EDID using the following protocol: • Write sequence, as defined in the Protocol for Main I C Port section •...

  • Page 193: Pcb Layout Recommendations

    Hardware User Guide UG-237 APPENDIX A PCB LAYOUT RECOMMENDATIONS The ADV7619 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board, in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV7619. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF and a 10 nF capacitor where possible.

  • Page 194: Digital Inputs

    UG-237 Hardware User Guide DIGITAL INPUTS The following digital inputs on the ADV7619 are 3.3 V inputs that are 5.0 V tolerant: • DDCA_SCL • DDCA_SDA • DDCB_SCL • DDCB_SDA Any noise that gets onto the HS and VS inputs trace will add jitter to the system. Therefore, the trace length should be minimized; and digital or other high frequency traces should not be run near it.

  • Page 195: Recommended Unused Pin Configurations

    Hardware User Guide UG-237 APPENDIX B RECOMMENDED UNUSED PIN CONFIGURATIONS Table 75. Recommended Configuration of Unused Pins Pin No. Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground CVDD Power HDMI Analog Block Supply Voltage (1.8 V) RXA_C- HDMI Input Float this pin RXA_C+...
  • Page 196 UG-237 Hardware User Guide Pin No. Mnemonic Type Recommended Configuration if Not Used Digital Output Float this pin Digital Output Float this pin Digital Output Float this pin DVDDIO Power Digital I/O Supply Voltage (3.3 V) DVDD Power Digital Core Supply Voltage (1.8 V) Digital Output Float this pin Digital Output...
  • Page 197 Hardware User Guide UG-237 Pin No. Mnemonic Type Recommended Configuration if Not Used Digital Output Float this pin Digital Output Float this pin Digital Output Float this pin SCLK/INT2 Digital Output Float this pin Digital Output Float this pin MCLK/INT2 Digital Output Float this pin DVDD...

  • Page 198: Added Endnote 1 To Table 76

    UG-237 Hardware User Guide APPENDIX C PIXEL OUTPUT FORMATS Table 76. SDR 4:2:2 Output Modes SDR 4:2:2 OP_FORMAT_SEL[7:0] 0x0A 8-Bit SDR 10-Bit SDR 12-Bit SDR 12-Bit SDR 12-Bit SDR ITU-R BT.656 ITU-R BT.656 ITU-R BT.656 ITU-R BT.656 ITU-R BT.656 Pixel Output Mode 0 Mode 0 Mode 0...
  • Page 199 Hardware User Guide UG-237 Table 77. SDR 4:2:2 Output Modes SDR 4:2:2 OP_FORMAT_SEL[7:0] 0x80 0x81 0x82 0x86 0x8A 16-Bit SDR 20-Bit SDR ITU-R BT.656 ITU-R BT.656 24-Bit SDR ITU-R 24-Bit SDR ITU-R 24-Bit SDR ITU-R Pixel Output Mode 0 Mode 0 BT.656 Mode 0 BT.656 Mode 1 BT.656 Mode 2...
  • Page 200 UG-237 Hardware User Guide Table 78. SDR 4:4:4 Output Modes SDR 4:4:4 OP_FORMAT_SEL[7:0] 0x40 0x41 0x42 0x46 Pixel Output 24-Bit SDR Mode 0 30-Bit SDR Mode 0 36-Bit SDR Mode 0 36-Bit SDR Mode 1 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z...
  • Page 201 Hardware User Guide UG-237 Table 79. DDR 4:2:2 Output Modes DDR 4:2:2 Mode (Clock/2) OP_FORMAT_SEL[7:0] 0x20 0x21 0x22 8-Bit DDR ITU-656 Mode 0 10-Bit DDR ITU-656 Mode 0 12-Bit DDR ITU-656 Mode 0 Pixel Output Clock Rise Clock Fall Clock Rise Clock Fall Clock Rise Clock Fall...
  • Page 202 UG-237 Hardware User Guide Table 80. DDR 4:4:4 Output Modes DDR 4:4:4 Mode (Clock/2) OP_FORMAT_SEL[7:0] 0x60 0x61 0x62 24-Bit DDR Mode 0 30-Bit DDR Mode 0 36-Bit DDR Mode 0 Pixel Output Clock Rise Clock Fall Clock Rise Clock Fall Clock Rise Clock Fall High-Z...

  • Page 203: Added Endnote 1 To Table 81

    Hardware User Guide UG-237 Table 81. Special SDR 4:2:2 and 4:4:4 Output Modes for Video with Pixel Clock Frequencies above 150 MHz 2 x SDR 4:2:2 Interleaved 2 x SDR 4:4:4 Interleaved OP_FORMAT_SEL[7:0] 0x94 0x95 0x96 0x54 2 × 16-Bits 2 ×...
  • Page 204 By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement.

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