Audio Codec Functionality; Audio Pll; Figure 116: High Level Overview Of Analog Audio Mux Input/Mux Output Configuration - Analog Devices ADV7850 Hardware Manual

ADV7850
Note: The analog audio input pins of the ADV7850 only see 880 mV RMS signals. However, the ADV7850 incorporates a gain stage to
restore the mux output level to 1.0 V rms. An external line driver is required to restore the audio output signals to the SCART
specification of 2.8 V rms.

Figure 116: High Level Overview of Analog Audio Mux Input/Mux Output Configuration

A factory calibration will be applied during final test to ensure that the gain through the mux circuit remains within +/-5%. Calibration is
also applied to the ADC reference current to ensure the code swing from the ADC remains within +/-5% across the part for a given input.
External impedances with a tolerance of +/-1% are required.
11.3

AUDIO CODEC FUNCTIONALITY

The ADV7850 supports an audio CODEC comprising a stereo ADC and a stereo DAC. The DAC output is available as a line level
output, and is also passed through an internal headphone amplifier. The output of the headphone amplifier can be used directly to drive
stereo headphones.
The audio CODEC requires an external MCLK. For an MCLK signal with a frequency of 3.072 MHz, 6.144 MHz, 12.288 MHz or 24.576
MHz, the ADC and DAC sample rates are 48 kHz. The user must ensure pll_ref_freq[1:0] is set correctly so that it always generates an
internal MCLK of 6.144 MHz. A fixed oversample rate of 128X is implemented.
If the MCLK is reduced to 2.8224 MHz, 5.6448 MHz, 11.2896 MHz or 22.5792 MHz the ADC and DAC sample rate will reduce to 44.1
kHz. The bandwidth of the digital filter is sufficient that a 20 kHz pass band is maintained in this mode.
The word depth of both ADC and DAC is 24 bits. The ADC and DAC have independent LRCLK and SCLK signals, but use a common
MCLK.
The ADC supports I2S mode, providing LRCLK, SCLK and I2S signals. These signals are sent to the HDMI Tx and embedded into the
HDMI stream. The DAC supports I2S mode. The LRCLK, SCLK and data signals must be provided by the back end SOC, and must be
frequency locked with the MCLK but phase independent. The output level is 1 V rms full scale.
There is one stereo headphone amplifier output capable of driving 32 Ω loads at 1 V rms. The headphone output incorporates circuitry to
suppress pop/click sounds during the power on/off cycle.

Audio PLL

11.3.1
The ADV7850 audio PLL generates the required internal analog and digital clocks for the audio CODEC. The PLL reference input signal
is selected using pll_ref_freq[1:0].
The audio PLL requires external components to operate correctly, as shown in Figure 117. The placement and layout of these
components should match the evaluation board layout.
The 1000 pF capacitor is an NPO type capacitor.
Rev. A May 2012 336