User Manuals: Analog Devices ADV7850 HDMI Receiver

Manuals and User Guides for Analog Devices ADV7850 HDMI Receiver. We have 1 Analog Devices ADV7850 HDMI Receiver manual available for free PDF download: Hardware Manual

Analog Devices ADV7850 Hardware Manual

Analog Devices ADV7850 Hardware Manual (458 pages)

Fast Switching 4:1 HDMI 1.4 Receiver With 3D-Comb Decoder and Digitizer

Brand: Analog Devices | Category: Receiver | Size: 6 MB

Table of Contents

Fast Switching 4:1 HDMI 1.4 Receiver with 3D-Comb Decoder and Digitizer

2
- Table of Contents
  2
- 1 Introduction to Adv7850 Hardware Manual
  
  11
  - Description of the Hardware Manual
    11
  - Copyright Information
    11
  - Disclaimer
    11
  - Trademark and Service Mark Notice
    11
  - Number Notations
    11
  - Register Access Conventions
    11
  - Acronyms and Abbreviations
    11
  - Control Description
    13
  - Figure 1: Field Description Format
    13
  - References
    14
- 2 Introduction
  
  15
  - Analog Front End
    15
  - Standard Definition Processor
    16
  - Hdmi Receiver
    16
  - Component Processor
    16
  - Audio Codec
    17
  - Main Features of Adv7850
    17
    
    Analog Front End
    17
    
    Composite and S-Video Processing
    17
    
    HDMI Receiver
    17
    
    Additional Features
    18
    
    Audio CODEC
    18
    
    Component Video Processing
    18
    
    RGB Graphics Processing
    18
  - Functional Block Diagram
    19
  - Figure 2: Functional Block Diagram
    19
  - Pin Description
    20
  - Figure 3: ADV7850 Pin Configuration
    20
  - Table 1: Function Descriptions
    20
- 3 Global Control Registers
  
  29
- 4 Primary Mode and Video Standard
  
  36
- 5 Analog Front End
  
  42
- 6 Standard Definition Processor
  
  69
  - Sdp Block
    69
  - Sdp Synchronization Processing
    69
  - Figure 16: Block Diagram of SDP
    69
  - Sdp General Setup
    70
    
    Autodetection of SDP Modes
    70
    
    Pedestal Configuration in SDP Modes
    72
  - Sdp Status Registers
    73
    
    SDP Autodetection Result
    73
    
    SDP Video Detection
    73
    
    Input Status
    74
    
    Macrovision Status
    77
    
    Synctip Noise Measurement, Noisy and very Noisy Signal Detection
    78
    
    Additional SDP Status Registers
    79
  - Sdp Color Controls
    80
    
    Brightness
    81
    
    Contrast
    81
    
    Hue
    81
    
    Saturation
    81
  - Sdp Gain Operation
    81
    
    Figure 17: SDP Gain Control Overview
    82
    
    SDP Luma Gain
    82
    
    Chroma Gain
    84
    
    Peak White Feature
    85
    
    Color Kill
    86
    
    Peak Chroma
    86
  - Comb
    87
    
    Comb Activation
    87
    
    Figure 18: 3D Comb and Motion Detection Operation
    87
    
    Comb Sensitivity
    92
  - Y Shaping Filter
    92
  - Figure 19: y Shaping Filter Flowchart
    94
  - Table 10: y Shaping Filter Selection
    95
  - Figure 20: y Shaping Filter Selection from No. 0 to No. 13 in Table 10
    97
  - Figure 21: y Shaping Filter Selection from No. 14 to 20 in Table 10
    98
  - Figure 22: y Shaping Filter Selection from No. 21 to 24 in Table 10
    98
  - Figure 23: y Shaping Filter Selection from No. 25 to 27 in Table 10
    99
  - Figure 24: y Shaping Filter Selection from No. 28 to 30 in Table 10
    99
  - Figure 25: y Shaping Filter Selection from No. 31 in Table 10
    100
    
    Input Shaping Filter Enables
    101
  - Chroma Shaping Filter
    103
  - Figure 26: C Shaping Filter Flowchart
    104
  - Table 11: C Shaping Filter Selection
    105
  - Figure 27: C Shaping Filter Selection No. 0 to 3 in Table 11
    106
  - Split Filter Selection
    107
  - Figure 28: C Shaping Filter Selection No. 4 to 13 in Table 11
    107
  - Figure 29: C Shaping Filter No. 14 to 18 in Table 11
    107
  - If Filter Compensation
    108
  - Figure 30: Split Filter Frequency Response
    108
  - Luma Transient Improvement and Chroma Transient Improvement
    109
  - Figure 31: if Compensation Filter Responses 0 to 3
    109
  - Figure 32: if Compensation Filter Responses 4 to 9
    109
  - Figure 33: LTI/CTI Operation Diagram
    110
  - Figure 34: SECAM Signal Distortion
    111
  - Figure 35: LTI Filter Response 0
    111
  - Figure 36: LTI Filter Response 1
    112
  - Figure 37: CTI Filter Response 0
    113
  - Figure 38: CTI Filter Response 1
    113
  - Ringing Reduction
    114
  - Horizontal and Vertical Peaking
    115
    
    Figure 39: Peaking Block Diagram
    115
    
    Horizontal Peaking
    115
    
    Figure 40: Core Threshold in Horizontal Peaking
    116
    
    Figure 41: Horizontal Peaking High-Pass Filter
    117
    
    Figure 42: Horizontal Peaking Band-Pass Filter 1
    117
    
    Figure 43: Horizontal Peaking Band-Pass Filter 2
    118
    
    Vertical Peaking
    118
    
    Figure 44: Peaking Controls
    119
    
    Figure 45: Vertical Peaking Filter
    120
    
    Figure 46: Frame Synchronization Block Diagram
    121
    
    Frame Synchronization (Frame Time Base Correction)
    121
  - Free Run Mode
    122
  - Letterbox Detection
    123
    
    Detection at End of Field
    124
    
    Detection at MID Range
    124
    
    Detection at Start of Field
    124
  - Sdp Synchronization Output Signals
    125
    
    Hsync Timing Configuration
    125
    
    Figure 47: Hsync and Vsync Timing Controls
    126
    
    Vsync and FIELD Configuration
    126
    
    DE Configuration
    129
    
    Csync Signal Configuration
    131
    
    Figure 48: de Timing Controls
    131
    
    Figure 49: Single CSC Channel
    132
    
    Manual Color Space Conversion Matrix
    132
    
    Table 12: CSC Coefficients
    132
    
    CSC Manual Programming
    135
- 7 Hdmi Receiver
  
  136
  - Modes of Operation
    136
    
    Figure 50: Functional Block Diagram of HDMI Core
    136
    
    HDMI Mux Mode
    136
    
    HDMI Non-Mux Mode
    136
  - Cable Detect
    137
  - Hot Plug Assert
    138
  - E-Edid/Repeater Controller
    141
  - E-Edid Data Configuration
    142
    
    E-EDID Support for Cable Supply Mode
    144
  - Supply
    144
  - Transitioning from Cable Supply Mode
    144
  - Spi Interface
    145
    
    Figure 51: SPI EEPROM Data Image Structure
    146
    
    SPI EEPROM Data Structure
    146
  - Structure of Internal E-Edid for Porta
    147
  - Structure of Internal E-Edid of Ports B, C, Andd
    147
  - Figure 52: Port a E-EDID Structure and Mapping
    147
  - Figure 53: Port B E-EDID Structure and Mapping for SPA Located in E-EDID Block 1
    148
  - Spa Configuration
    150
  - External E-Edid
    150
  - Tmds Equalization
    150
    
    Equalizer Read Back
    150
    
    Manual Operation
    150
  - Port Selection
    151
  - Fast Switching and Background Port Selection
    151
  - Tmds Clock Activity Detection
    153
    
    Clock and Data Termination Control
    154
  - Tmds Measurement
    155
    
    TMDS Measurement after TMDS PLL
    155
  - Deep Color Mode Support
    158
  - Figure 54: Monitoring TMDS Clock Frequency
    158
  - Video Fifo
    160
  - Figure 55: HDMI Video FIFO
    160
  - Pixel Repetition
    161
  - Arc Support
    163
  - Video Support
    165
  - Hdcp Support
    165
    
    HDCP Decryption Engine
    165
    
    HDCP Keys Access Flags
    167
    
    Internal HDCP Key OTP ROM
    167
    
    Figure 56: HDCP ROM Access after Power up
    168
    
    Figure 57: HDCP ROM Access after KSV Update from the Transmitter
    168
  - Hdmi Synchronization Parameters
    169
    
    Horizontal Filter and Measurements
    169
    
    Primary Port Horizontal Filter Measurements
    169
    
    Background Port Horizontal Filter Measurements
    171
    
    Figure 58: Horizontal Timing Parameters
    171
    
    Horizontal Filter Locking Mechanism
    172
    
    Primary Port Vertical Filter Measurements
    172
    
    Vertical Filters and Measurements
    172
    
    Figure 59: Vertical Parameters for Field 0
    174
    
    Background Port Vertical Filter Measurements
    176
    
    Figure 60: Vertical Parameters for Field 1
    176
    
    Vertical Filter Locking Mechanism
    177
  - Audio Control and Configuration
    177
    
    ACR Parameters Loading Method
    178
    
    Audio DPLL
    178
    
    Figure 61: Audio Processor Block Diagram
    178
    
    Locking Mechanism
    178
    
    Audio DPLL Coast Feature
    179
  - Audio Fifo
    179
  - Figure 62: Audio FIFO
    179
  - Table 13: Selectable Coast Conditions
    179
  - Audio Packet Type Flags
    181
  - Audio Output Interface
    183
  - Figure 63: Monitoring Audio Packet Type Processed by ADV7850
    183
  - Table 14: Audio Outputs and Clocks
    183
    
    I2S/SPDIF Audio Interface and Output Controls
    184
    
    Table 15: Default Audio Output Pixel Port Mapping
    184
    
    Table 16: Audio Mappings for I2S_Spdif_Map_Rot = 00, I2S_Spdif_Map_Inv = 0 (Default)
    184
    
    Table 17: Audio Mappings for I2S_Spdif_Map_Rot = 00, I2S_Spdif_Map_Inv = 1
    184
    
    Figure 64: Timing Audio Data Output in I
    186
    
    Figure 65: Timing Audio Data Output in Right Justified Mode
    186
    
    Figure 66: Timing Audio Data Output in Left Justified Mode
    186
    
    Figure 67: IEC 60958 Sub-Frame Timing Diagram
    186
    
    Table 18: I S/SPDIF Interface Description
    186
    
    DSD Audio Interface and Output Controls
    187
    
    Figure 68: AES3 Sub-Frame Timing Diagram
    187
    
    Figure 69: AES3 Stream Timing Diagram
    187
    
    Table 19: DSD Interface Description
    187
    
    Figure 70: DSD Timing Diagram
    188
    
    Table 20: Audio Mapping for Dsd_Map_Rot = 00, Dsd_Map_Inv = 0 (Default)
    188
    
    Table 21: Audio Mapping for Dsd_Map_Rot = 00, Dsd_Map_Inv = 1
    188
    
    DST Audio Interface and Output Controls
    189
    
    Figure 71: DST Timing Diagram for DST_DOUBLE = 0
    189
    
    Table 22: DST Interface Description
    189
    
    Figure 72: DST Timing Diagram for DST_DOUBLE = 1
    190
    
    HBR Interface and Output Controls
    190
    
    Table 23: HBR Interface Description
    190
  - Mclkout Setting
    191
  - Audio Channel Mode
    191
  - Audio Muting
    192
    
    Audio Mute Configuration
    192
    
    Table 24: Selectable Mute Conditions
    193
    
    Audio Stream with Incorrect Parity Error
    194
    
    AV Mute Status
    194
    
    Internal Mute Status
    194
  - Audio Clock Regeneration Parameters
    195
    
    ACR Parameters Readbacks
    195
    
    Monitoring ACR Parameters
    195
  - Channel Status
    196
    
    Validity Status Flag
    196
    
    Figure 73: Reading Valid Channel Status Flags
    197
    
    General Control and Mode Information
    197
    
    Category Code
    198
    
    Sampling and Frequency Accuracy
    198
    
    Source Number and Channel Number
    198
    
    Channel Status Copyright Value Assertion
    199
    
    Word Length
    199
    
    Monitoring Change of Audio Sampling Frequency
    200
  - Packets and Infoframes Registers
    200
    
    Infoframe Checksum Error Flags
    201
    
    Infoframe Collection Mode
    201
    
    Infoframes Registers
    201
    
    AVI Infoframe Registers
    202
    
    Table 25: AVI Infoframe Registers
    202
    
    Audio Infoframe Registers
    203
    
    Table 26: Audio Infoframe Registers
    203
    
    MPEG Source Infoframe Registers
    204
    
    SPD Infoframe Registers
    204
    
    Table 27: SPD Infoframe Registers
    204
    
    Table 28: MPEG Infoframe Registers
    205
    
    Table 29: VS Infoframe Registers
    205
    
    Vendor Specific Infoframe Registers
    205
    
    Multiple Infoframes Support ( THX Media Director™)
    206
  - Packet Registers
    207
    
    ACP Packet Registers
    207
    
    Table 30: ACP Packet Registers
    207
    
    ISRC Packet Registers
    208
    
    Table 31: ISRC1 Packet Registers
    208
    
    Table 32: ISRC2 Packet Registers
    209
    
    Gamut Metadata Packets
    210
    
    Table 33: Gamut Metadata Packet Registers
    210
  - Customizing Packet/Infoframe Storage Registers
    211
  - Background Port Infoframe and Packet Support
    213
  - Repeater Support
    214
    
    Repeater Routines Performed by the E-Edid/Repeater Controller
    214
    
    Repeater Actions Required by External Controller
    215
    
    HDCP Registers Available in Repeater Map
    216
    
    Table 34: Register Location for SHA_1 Hash Value
    218
    
    Table 35: KSV List Bytes
    218
  - Interface to DCM Section
    221
  - Figure 74: YC
    221
    
    Color Space Information Sent to the Cp Section
    222
  - Status Registers
    222
  - Figure 75: Video Stream Output by HDMI Core for YC
    222
  - Table 36: HDMI Flags in IO Map Register 0X60
    223
  - Table 37: HDMI Flags in IO Map Register 0X65
    223
  - Table 38: HDMI Flags in IO Map Register 0X6A
    223
  - Table 39: HDMI Flags in IO Map Register 0X6F
    223
  - Table 40: HDMI Flags in IO Map Register 0X74
    223
  - Table 41: HDMI Flags in IO Map Register 0X79
    224
  - Table 42: HDMI Flags in IO Map Register 0X7E
    224
  - Table 43: HDMI Flags in IO Map Register 0X83
    224
  - Hdmi Receiver Section Reset Strategy
    225
  - Hdmi Packet Detection Flag Reset
    225
  - Table 44: HDMI Infoframe Checksum Error Flags in IO Map
    225
  - Table 45: AKSV Update Flags in IO Map Register 0X88
    225
  - Table 46: HDMI Flags in HDMI Map
    225
- 8 Decimation Controls, Color Space Conversion, and Color Controls
  
  226
  - DCM Configuration
    226
  - Manual Filter Coefficient Programming
    227
    
    DCM Channel Power down Control
    229
  - Color Space Conversion Matrix
    230
    
    CP CSC Selection
    230
    
    Figure 76: Configuring CP CSC Block
    230
    
    Automatic Color Space Conversion Matrix
    231
    
    Selecting Automatic or Manual CP CSC Conversion Mode
    231
    
    Table 47: Automatic Input Color Space Selection
    232
    
    Table 48: Automatic CSC Selection
    232
    
    Figure 77: Single CSC Channel
    233
    
    Manual Color Space Conversion Matrix
    233
    
    Table 49: CSC Configuration for All CSC Modes Reported by Csc_Coeff_Sel_Rb
    233
    
    Table 50: CSC Coefficients
    234
    
    CSC Manual Programming
    236
    
    CSC Example
    237
    
    CSC in Pass-Through Mode
    238
  - Color Controls
    238
- 9 Component Processor
  
  241
- 10 Vbi Data Processor
  
  310
- 11 Audio Codec
  
  333
- 12 Memory Controller
  
  344
  - Memory Requirements
    344
  - General Controls
    344
    
    Output Enables
    344
    
    Reset
    344
  - Drive Strength Controls
    345
  - Ddr2 bist Test
    345
  - Figure 121: DDR2 bist Test Architecture
    346
  - External Memory Layout Guidelines
    347
- 13 Hdmi Transmitter
  
  349
  - General Operation
    349
  - General Controls
    349
  - Figure 122: Functional Block Diagram of HDMI Tx Core
    349
  - Hdmi DVI Selection
    350
  - Av Mute
    351
  - Tx Squelch Feature
    351
  - Table 82 : TX Squelch Configuration Options
    351
  - Source Product Description Infoframe
    352
  - Table 83: SPD Infoframe Configuration Register
    352
  - Spare Packets
    353
  - Table 84: Spare Packet 1 Configuration Register
    353
  - System Monitoring
    354
    
    General Status and Interrupts
    354
    
    Table 85: Spare Packet 2 Configuration Register
    354
  - Edid/Hdcp Controller Status
    355
  - Edid/Hdcp Controller Error Codes
    355
  - Table 86: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0X96
    355
  - Table 87: HDMI Tx Interrupt Bits in Main Map Register 0X97
    355
  - Table 88: Status Bits in Main Map Register 0X42
    355
  - Video Setup
    356
    
    Figure 123: Format of Video Data Input into HDMI Tx Core
    356
    
    Input Format
    356
    
    Video Mode Detection
    356
    
    Pixel Repetition
    357
    
    AVI Infoframe
    358
    
    Video Related Packets and Infoframes
    358
    
    MPEG Infoframe
    359
    
    Table 89: AVI Infoframe Configuration Registers
    359
    
    Gamut Metadata
    360
    
    Table 90: MPEG Infoframe Configuration Registers
    360
    
    Figure 124: I C Write Timing if GMP Data
    361
    
    Table 91: Gamut Metadata Packet Configuration Registers
    361
  - Audio Setup
    362
    
    Input Format
    362
    
    Table 92: Valid Configuration for Audio_Mode[1:0]
    362
    
    I2S Audio
    363
    
    Table 93: Audio Input Format Summary
    363
    
    Figure 125: IEC60958 Sub Stream
    367
    
    Figure 126: AES3 Stream Format Input to ADV7850
    367
    
    Figure 127: Timing of Standard I2S Stream Input to ADV7850
    367
    
    Figure 128: Timing for Right-Justified I2S Stream Input to ADV7850
    368
    
    Figure 129: Timing for Left-Justified I2S Stream Input to ADV7850
    368
    
    Figure 130: Timing for I2S Stream in 32-Bit Mode
    368
    
    Figure 131: Timing for I2S Stream in Left or Right-Justified and 32-Bit Modes
    368
    
    SPDIF Audio
    368
    
    DSD Audio
    369
    
    HBR Audio
    369
    
    Table 94: Valid Configuration for Audioif_Sf[2:0]
    369
    
    Figure 132: Audio Clock Regeneration
    370
    
    N and CTS Parameters
    370
    
    CTS Parameter
    371
    
    N Parameter
    371
    
    Recommended N and Expected CTS Values
    371
    
    Table 95: Recommended N and Expected CTS Values for 32 Khz Audio
    372
    
    Table 96: Recommended N and Expected CTS Values for 44.1 Khz and Multiples
    372
    
    Audio Sample Packets
    373
    
    Table 97: Recommended N and Expected CTS Values for 48 Khz and Multiples
    373
    
    Table 98: I 2 S Channel Status ADV7850 Register Map Location of Fixed Value
    375
    
    Audio Infoframe
    377
    
    Figure 133: Definition of Channel Status Bits 20 to 23
    377
    
    Audio Content Protection Packet
    378
    
    Table 100: ACP Packet Configuration Registers
    378
    
    Table 99: Audio Infoframe Configuration Registers
    378
    
    ISRC Packet
    379
    
    Table 101: ISRC1 Packet Configuration Registers
    379
  - Edid Handling
    380
    
    Reading the EDID
    380
    
    Table 102: ISRC2 Packet Configuration Registers
    380
    
    Additional Segments
    381
    
    EDID Definitions
    381
    
    Figure 134: Reading Sink EDID through ADV7850
    381
    
    EDID_REREAD Control
    382
    
    EDID_TRIES Control
    382
  - Hdcp Handling
    382
    
    One Sink and no Upstream Devices
    382
    
    Multiple Sinks and no Upstream Devices
    384
    
    Table 103: KSV Fields Accessed from EDID Map
    384
    
    Software Implementation
    385
    
    AV Mute
    386
    
    Figure 135: HDCP Software Implementation
    386
- 14 Register Access and Serial Ports Description
  
  388
  - Maini 2 C Port
    388
    
    Figure 136: ADV7850 Register Map Access through Main I
    388
    
    Register Access
    388
    
    Table 104: Register Maps and I
    388
    
    Protocol for Main I C Port
    389
  - DDC Ports
    389
    
    Figure 137: Bus Data Transfer
    389
    
    Figure 138: Read and Write Sequence
    389
    
    I 2 C Protocols for Access to the Internal E-EDID
    389
    
    C Protocols for Access to HDCP Registers
    390
    
    DDC Port a
    390
    
    DDC Port B
    390
    
    Figure 139: Current Address Read Sequence
    390
    
    Figure 140: Internal E-EDID and HDCP Registers Access from Port a
    390
    
    Figure 141: Internal E-EDID and HDCP Registers Access from Port B
    390
    
    DDC Port C
    391
    
    DDC Port D
    391
    
    Figure 142: Internal E-EDID and HDCP Registers Access from Port C
    391
    
    Figure 143: Internal E-EDID and HDCP Registers Access from Port D
    391
- 15 Interrupts
  
  392
  - Interrupt Architecture Overview
    392
  - Interrupt Pins
    392
    
    Interrupt Drive Level
    392
    
    Interrupt Duration
    392
    
    Interrupt Manual Assertion
    393
    
    Multiple Interrupt Events
    394
  - Rx Section
    394
  - Figure 144: Level and Edge-Sensitive Raw, Status and Interrupt Generation
    396
  - Figure 145: AVI_INFO_RAW and AVI_INFO_ST Timing
    397
  - Figure 146: NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing
    397
  - Description of Rx Interrupt Bits
    398
    
    Analog/Hdmi Video Mode
    398
    
    General Operation
    398
    
    HDMI Only Mode
    398
    
    Macrovision Detection
    398
    
    VDP Operation
    398
  - Additional Explanations
    400
    
    Afe_Interrupt_Raw
    400
    
    Figure 147: Suggested Method of Handling Afe_Interrupt
    401
    
    Cp_Lock, Cp_Unlock
    402
    
    Stdi_Data_Valid_Raw
    402
    
    Group 1 HDMI Interrupts
    403
    
    Group 2 HDMI Interrupts
    403
    
    Group 3 HDMI Interrupts
    403
    
    HDMI Interrupts Validity Checking Process
    403
    
    Table 105: HDMI Interrupts Group 1
    403
    
    Table 106: HDMI Interrupts Group 2
    403
    
    Video 3D Detection
    403
    
    Interrupt Status Registers
    404
    
    Storing Masked Interrupts
    404
    
    Table 107: HDMI Interrupts Group 3
    404
    
    Processing Analog Front End Interrupts
    425
  - Tx Core
    426
    
    Figure 148: Processing Trilevel Interrupts
    426
    
    Interrupt Architecture Overview
    426
    
    Interrupt Bits
    427
    
    Interrupt Mask Bits
    428
  - Pcb Layout Recommendations
    429
  - Analogue Interface Inputs
    429
  - Power Supply Bypassing
    429
  - Figure 149: Recommended Power Supply Decoupling
    429
- 16 Appendix A
  
  429
List of Figures

450
- List of Tables
  
  454
- List of Equations
  
  457
- Revision History
  
  458

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