Analog Devices ADV7850 Hardware Manual page 451

ADV7850
Figure 50: Functional Block Diagram of HDMI Core ................................................................................................................................. 136
Figure 51: SPI EEPROM Data Image Structure ............................................................................................................................................ 146
Figure 52: Port A E-EDID Structure and Mapping ...................................................................................................................................... 147
Figure 53: Port B E-EDID Structure and Mapping for SPA Located in E-EDID Block 1 ....................................................................... 148
Figure 54: Monitoring TMDS Clock Frequency ........................................................................................................................................... 158
Figure 55: HDMI Video FIFO ......................................................................................................................................................................... 160
Figure 56: HDCP ROM Access After Power Up ........................................................................................................................................... 168
Figure 57: HDCP ROM Access After KSV Update from the Transmitter ................................................................................................ 168
Figure 58: Horizontal Timing Parameters ..................................................................................................................................................... 171
Figure 59: Vertical Parameters for Field 0 ..................................................................................................................................................... 174
Figure 60: Vertical Parameters for Field 1 ..................................................................................................................................................... 176
Figure 61: Audio Processor Block Diagram .................................................................................................................................................. 178
Figure 62: Audio FIFO ...................................................................................................................................................................................... 179
Figure 63: Monitoring Audio Packet Type Processed by ADV7850 .......................................................................................................... 183
Figure 64: Timing Audio Data Output in I S Mode ..................................................................................................................................... 186
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Figure 65: Timing Audio Data Output in Right Justified Mode ................................................................................................................. 186
Figure 66: Timing Audio Data Output in Left Justified Mode ................................................................................................................... 186
Figure 67: IEC 60958 Sub-frame Timing Diagram ....................................................................................................................................... 186
Figure 68: AES3 Sub-frame Timing Diagram ............................................................................................................................................... 187
Figure 69: AES3 Stream Timing Diagram ..................................................................................................................................................... 187
Figure 70: DSD Timing Diagram .................................................................................................................................................................. 188
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Figure 71: DST Timing Diagram for DST_DOUBLE = 0 .......................................................................................................................... 189
Figure 72: DST Timing Diagram for DST_DOUBLE = 1 ........................................................................................................................... 190
Figure 73: Reading Valid Channel Status Flags............................................................................................................................................. 197
Figure 74: YC C 4:2:2 Video Data Encapsulated in HDMI Stream .......................................................................................................... 221
b r
Figure 75: Video Stream Output by HDMI Core for YC C 4:2:2 Input and UP_CONVERSION = 0 ................................................ 222
b r
Figure 76: Configuring CP CSC Block ........................................................................................................................................................... 230
Figure 77: Single CSC Channel ........................................................................................................................................................................ 233
Figure 78: Component Processor Block Diagram ........................................................................................................................................ 241
Figure 79: Position of Voltage Clamp Window ............................................................................................................................................ 242
Figure 80: CP Automatic Gain Controls ........................................................................................................................................................ 245
Figure 81: Channel A, B, and C Automatic Value Selection ....................................................................................................................... 252
Figure 82: CP DATA Path Channel A (Y) for Analog Mode ...................................................................................................................... 255
Figure 83: CP Data Path Channel B/C (UV) for Analog Mode .................................................................................................................. 256
Figure 84: CP Data Path Channel A/B/C (RGB) for Analog Mode ........................................................................................................... 257
Figure 85: Sliced Signal Path ........................................................................................................................................................................... 258
Figure 86: External/HDMI Syncs Routing to CP Section ........................................................................................................................... 259
Figure 87: Final Sync Muxing Stage ............................................................................................................................................................... 262
Figure 88: SSPD Auto Detection Flowchart .................................................................................................................................................. 264
Figure 89: SSPD VSync and HSync Monitoring Operation ........................................................................................................................ 270
Figure 90: STDI Horizontal Locking Operation ........................................................................................................................................... 274
Figure 91: STDI HSync Monitoring Operation ............................................................................................................................................ 274
Figure 92: STDI Vertical Locking Operation ................................................................................................................................................ 275
Figure 93: STDI VSync Monitoring Operation............................................................................................................................................. 275
Figure 94: STDI Usage Flowchart ................................................................................................................................................................... 277
Figure 95: ADV7850 Simplified Synchronization Signal Processing Flow Diagram .............................................................................. 278
Figure 96: Synchronization Repositioning and Displayed Area ................................................................................................................. 279
Figure 97: HS Timing ........................................................................................................................................................................................ 281
Figure 98: 525i VS Timing ............................................................................................................................................................................... 289
Figure 99: 625i VS Timing ............................................................................................................................................................................... 290
Figure 100: 525p VS Timing ............................................................................................................................................................................ 291
Figure 101: 625p VS Timing ............................................................................................................................................................................ 292
Rev. A May 2012 451