Stdi Readback Values For Graphics Standards; Cp Output Synchronization Signal Positioning; Figure 95: Adv7850 Simplified Synchronization Signal Processing Flow Diagram; Table 54: Stdi Results For Graphics Standards - Analog Devices ADV7850 Hardware Manual

9.7.3.5 STDI Readback Values for Graphics Standards

Standard
XGA 85
SXGA 60
XGA 75
XGA 70
SVGA 85
XGA 60
SVGA 72
SVGA 75
VGA 85
VGA 72
SVGA 60
VGA 75
SVGA 56
VGA 60

9.8 CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING

The ADV7850 overall synchronization processing flow is shown in the block diagram in
synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits marked in red
in Figure 95.
PRIM_MODE[2]
SYNC_CH1_HS_SEL[1:0]
SYNC_CH1_VS_SEL[1:0]
SYNC_CH1_SOG_SEL[1:0]
SYNC1
SYNC2
SYNC3
SYNC4
HS_IN1
VS_IN1
HS_IN2
VS_IN2
PRIM_MODE[2]
SYNC_CH2_HS_SEL[1:0]
SYNC_CH2_VS_SEL[1:0]
SYNC_CH2_SOG_SEL[1:0]
HDMI Port A
TMDS PLL
HDMI Port B
HDMI Port C
HDMI Port D
HDMI Block
As shown in Figure 95, the ADV7850 CP can output the following three primary and two secondary synchronization signals, which are
controlled by the output control block in the CP block. These timing signals are sent to the HDMI Tx section.
Primary:
• Horizontal synchronization timing reference output on the HS/CS pin
•
Vertical synchronization timing reference output on the VS/FIELD pin
• Field timing reference output on the FIELD/DE pin or as a secondary signal on the VS/FIELD pin
Rev. A May 2012

Table 54: STDI Results for Graphics Standards

CHx_BL[13:0]
27 MHz XTAL
3137
3367
3590
3817
4016
4456
4484
4599
4984
5694
5694
5750
6136
6856
SYNC CHANNEL 1
HS/CS 1
HS/CS 1_GR
VS1
SSPD
SYNC MUX 1
VS1_GR
BLOCK1
EMB_SYNC_1
EMB_SYNC_1_GR
HS1_GR_PC
STDI
VS1_GR_PC
BLOCK1
HS2_GR_PC
STDI
VS2_GR_PC
BLOCK2
HS/CS 2
HS/CS 2_GR
SYNC MUX 2
VS2
SSPD
VS2_GR
BLOCK2
EMB_SYNC_2
EMB_SYNC_2_GR
SYNC CHANNEL 2

Figure 95: ADV7850 Simplified Synchronization Signal Processing Flow Diagram

CHx_LCF[10:0] CHx_LCVS[4:0]
805 to 808 0 to 3
1063 to 1066 0 to 3
797 to 800 0 to 3
800 to 806 0 to 6
628 to 631 0 to 3
800 to 806 0 to 6
660 to 666 0 to 6
622 to 625 0 to 3
506 to 509 0 to 3
517 to 520 0 to 3
624 to 628 0 to 4
497 to 500 0 to 3
623 to 625 0 to 2
523 to 525 0 to 2
EMBEDDED_
SYNC_MODE1
HS1_PC
VS1_PC
EMBEDDED_
SYNC_MODE
HS/CS
VS
EMBEDDED_
SYNC_MODE2
LLC
HS2_PC
Generation
VS2_PC
Sync
LLC
Conditioning
HDMI_Pixel_Clk
VID_STD
PRIM_MODE
278
FCL[12:0]
27 MHz XTAL
1240
1761
1407
1507
1240
1761
1465
1407
1240
1465
1761
1407
1883
1761
Figure 95. The user can reposition the
ADV7850
LLC
SYNC_OUT
HS/CS
VS/FIELD
FIELD/DE