Audio Dpll Coast Feature; Audio Fifo; Figure 62: Audio Fifo; Table 13: Selectable Coast Conditions - Analog Devices ADV7850 Hardware Manual

Audio DPLL Coast Feature

7.25.4
The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio master clock when selectable events occur.
The coast feature allows the audio DPLL to provide an audio master clock when the audio processor mutes the audio following a mute
condition (refer to Section 7.31). The events that cause the audio DPLL to coast are selected via the coasts masks listed in
Bit Name
ac_msk_vclk_chng
ac_msk_vpll_unlock
ac_msk_new_cts
ac_msk_new_n
ac_msk_chng_port
ac_msk_vclk_det

7.26 AUDIO FIFO

The audio FIFO can store up to 128 audio stereo data from the audio sample, DSD, DST or HBR packets. Stereo audio data are added into
the FIFO from the audio packet received. Stereo audio data are retrieved from the FIFO at a rate corresponding to 128 times the audio
sampling frequency, f .
s
The status of the audio FIFO can be monitored through the status flags fifo_underflo_raw, fifo_overflo_raw, fifo_near_ovfl_raw, and
fifo_near_uflo_raw.
Rev. A May 2012

Table 13: Selectable Coast Conditions

HDMI Description
Map Address
0x13[6] When set to 1, audio DPLL coasts if TMDS clock
has any irregular/missing pulses
0x13[5] When set to 1, audio DPLL coasts if TMDS PLL
unlocks
0x13[3] When set to 1, audio DPLL coasts if CTS changes
by more than threshold set in
cts_change_threshold[5:0]
0x13[2] When set to 1, audio DPLL coasts if N changes
0x13[1] When set to 1, audio DPLL coasts if active port is
changed
0x13[0] When set to 1, audio DPLL coasts if no TMDS
clock is detected on the active port
Address Order
Steoro Data N-1
Stereo Data N-2
Steoro Data 1
Steoro Data 0
Empty
Address 127
.
.
.
Empty
Address N+2
Address N+1
Address N
.
.
.
Address 3
Address 2
Empty
Address 1
Empty
Address 0

Figure 62: Audio FIFO

179
Corresponding Status
Registers(s)
vclk_chng_raw
tmds_pll_locked
cts_pass_thrsh_raw
change_n_raw
hdmi_port_select[2:0]
tmds_clk_a_raw
tmds_clk_b_raw
tmds_clk_c_raw
tmds_clk_d_raw
Write Pointer
Read Pointer
ADV7850
Table 13.