Signal Routed To Sspd Blocks - Analog Devices ADV7850 Hardware Manual

each input. Each output has two instances, one with the same name as the input, and one with _GR at the end of the name. The _GR
signals are latched by the XTAL clock and have a digital filter applied to them, whereas the output signals with the same name as the input
signals are true bypass versions of the input signals; they are not latched by XTAL and they do not have any filtering applied to them.
The _GR signals will have a glitch rejection filter applied to them. The filter can be controlled by the
dig_sync_deglitch_reduce_man
When dig_sync_deglitch_reduce_man
wide for component inputs up to and including 1080i, and sync signals that are less than two XTAL clocks wide for component input
1080p and graphics standards. When this bit is set to 1, the user can select the filter to reduce syncs that are less than five XTAL clocks
wide, or less than two XTAL clocks wide by setting
dig_sync_deglitch_reduce, Addr 44 (CP), Address 0xF5[3]
This control is used to configure the deglitch filters that process synchronization signals before they are input to the SSPD section. The
value set is effective if dig_sync_deglitch_reduce_man is set to 1.
Function
dig_sync_deglitch_redu
ce
1
0 
dig_sync_deglitch_reduce_man, Addr 44 (CP), Address 0xF5[2]
This control is used to manually configure the deglitch filters that process synchronization signals input to the SSPD sections.
Function
dig_sync_deglitch_redu
ce_man
1
0 

9.6.2.3 Signal Routed to SSPD Blocks

The SSPD block from each synchronization channel receives six input signals, namely HS, HS_GR, VS, VS_GR, EMB_SYNC, and
EMB_SYNC_GR. SSPD analyses the _GR signals to determine which signals have valid sync information, and will 'correct' the polarity of
the syncs. In this instance, the definition of a 'correct' sync polarity is 'negative going' , so for input formats with positive going syncs, these
syncs will be inverted. The outputs from the SSPD section are the signals whose names end with _PC. These signals are the polarity
corrected version of the syncs signals input to the SSPD sections.
The SSPD block will pass a corrected, registered, glitch rejected HSync and VSync signal to the STDI block. Note that for embedded sync
inputs or external CSync inputs where both HSync and VSync information are contained in one signal, the same signal will be applied to
both inputs of the STDI block.
The SSPD block will also pass a corrected HS and VS signal to the final mux shown on the right side of
EMBEDDED_SYNC_MODE which tells the CP core if the source of the HS_PC and VS_PC signals are from an embedded signal or
separate signals. These syncs are polarity corrected but are not XTAL registered, nor are they glitch rejected.
The final mux shown in Figure 86
and sync channel 2. Various controls exist to select how the SSPD block works, and which sync channel is passed to the CP core. These
controls are described in detail in Section 9.7.
Note that the syncs signals VS_PC and HS_PC passed to the CP core are polarity corrected but not XATL registered and glitch rejected.
However, internally in the CP core, a glitch rejection filter is applied which rejects any sync signals less than seven CP clocks in width.
Rev. A May 2012
signals.
is set to 0, the block automatically removes any sync signals that are less than five XTAL clocks
dig_sync_deglitch_reduce
Description
Remove 2 xtal clock wide glitches from synchronization signals input to SSPD sections
Remove 5 xtal clock wide glitches from synchronization signals input to SSPD sections
Description
Manual configuration: deglitch filters configured via dig_sync_deglitch_reduce
Automatic configuration: deglitch filters remove 5 xtal clock wide glitches from
synchronization signals input to SSPD section
selects between the HSync and VSync (and embedded sync information signal) from sync channel 1
to 0 or 1 respectively.
261
ADV7850
dig_sync_deglitch_reduce
Figure 86, as well as a signal called
and