•
Primary mode should be configured for SDP and HDMI audio mode (prim_mode[3:0] set to 0x04)
•
ADC simultaneous mode should be enabled (adc_hdmi_simult_mode set to 0x01).
•
The desired 2x1 SDP mode should be configured by setting vid_std[5:0]
2x1 CVBS (vid_std[5:0] set to 0x00)
2x1 YC (vid_std[5:0] set to 0x08)
2x1 YPrPb (vid_std[5:0] set to 0x10)
•
Select Clocking mode for Audio to the output.
IO Map Register 0xD9 to a value of 0x09. This configures the mode to CVBS + HDMI Audio.
IO Map Register 0xD8 to a value of 0x10. This enables the manual clocking mode
4.3 PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN
To support Free run in HDMI Mode, the ADV7850 must use the CP core. Free Run is only supported up to 225MHz. If free run is
enabled in HDMI mode, PRIM_MODE [3:0] and VID_STD [5:0] should be used to specify the output resolution to which the ADV7850
free runs. Along with specifying the standard to free run to from the HDMI Non-Mux mode standards, DIS_AUTO_PARAM_BUFFER
should be set to 1 also.
Rev. A May 2012
41
ADV7850
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