Analog Front End; Adc Sampling Clock; Adcs And Voltage Clamps; Analog Input Hardware Configuration - Analog Devices ADV7850 Hardware Manual

5 ANALOG FRONT END

The analog front end (AFE) comprises the following:
• High performance 12-bit analog to digital converters (ADCs) with clamping circuitry
• Thirteen analog inputs and multiplexing capability
•
Three synchronization (SYNC1, SYNC2 and SYNC3) input multiplexers with synchronization slicers and filtering
• Variable bandwidth anti aliasing filters
•
LLC-DLL (Line Locked Clock – Delay Locked Loop)
• Eight trilevel input detection blocks

5.1 ADC SAMPLING CLOCK

The ADV7850 has two main modes of operation for sampling the input analog video: CP mode and SDP mode. This is determined by the
primary mode setting.
• When the SDP is enabled, fixed 108 MHz sampling is applied to the ADCs. The SDP processes the video signal and, using a line
length tracking processor, resamples the incoming video so that 720 active pixels are always generated per line. Note that no user
I C settings are available for the PLL when in SDP mode as the PLL is controlled directly by the SDP.
2
• When the CP is enabled, true line locked sampling is applied to the video signal being processed. This means that the horizontal
synchronization signal of the incoming video signal is applied to the PLL and multiplied by the desired number of samples per
line, which yields the pixel sampling clock used in CP mode.
The CP ADC sampling clock is a line locked clock that is generated automatically by a digital encoder synthesizer. The following controls
enable the user to adjust the ADC sampling clock:
pll_div_man_en, Addr A0 (VFE), Address 0x16[7]
This control is used to manually override the PLL divider ratio value.
Function
pll_div_man_en
0 
1
pll_div_ratio[12:0], Addr A0 (VFE), Address 0x16[4:0]; Address 0x17[7:0]
This control is used to set the manual PLL divide ratio. It is sequenced and requires sequential writes for the desired value to be
updated.
Function
pll_div_ratio[12:0]
xxxxxxxxxxxxx

5.2 ADCS AND VOLTAGE CLAMPS

Analog Input Hardware Configuration

5.2.1
The ADV7850 supports 13 analog inputs. The analog inputs have an input range of 0 to 1 V.
Rev. A May 2012
Description
Disable manual PLL divider ratio settings. PLL divider ratio set by prim_mode[3:0] and
vid_std[5:0].
Set pll_div_ratio manually as defined by pll_div[12:0].
Description
Synthesizer feedback value. pll_man_val_en must be set for this value to be active.

Figure 5: Analog Inputs Hardware Configuration

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ADV7850