Structure Of Internal E-Edid For Porta; Structure Of Internal E-Edid Of Ports B, C, Andd; Figure 52: Port A E-Edid Structure And Mapping - Analog Devices ADV7850 Hardware Manual

7.9 STRUCTURE OF INTERNAL E-EDID FOR PORT A
The internal E-EDID is enabled on Port A by setting
the DDC line of Port A is shown in
The image of the internal E-EDID that is accessed on the DDC bus of Port A corresponds to the data image contained in the internal E-
EDID RAM.
Notes:
•
After man_edid_a_enable
image for Port A and updates the internal RAM address locations 0x7F, 0xFF, 0x17F, 0x1FF, 0x27F and 0x2FF in the internal E-
EDID RAM with the computed checksums.
•
After power up, the ADV7850 E-EDID/Repeater controller sets all bytes in the internal E-EDID RAM to 0. This operation takes
less than 1 msec. It is recommended to wait for at least 1 ms before initializing the EDID Map with an E-EDID image.
•
When internal E-EDID is enabled on Port A, the Hot Plug should not be asserted until the EDID Map has been completely
initialized with E-EDID.
• The internal E-EDID can be accessed in read-only mode through the DDC interface at the I
• The internal E-EDID can be accessed in read/write mode through the general I
7.10 STRUCTURE OF INTERNAL E-EDID OF PORTS B, C, AND D
This section describes the structure of the internal E-EDID accessible through the DDC bus of Port B. The same description applies to the
structure and configuration of the internal E-EDID accessed through Port C and Port D.
The internal E-EDID is enabled for Port B by setting
DDC bus of Port B corresponds to the data image contained in the internal E-EDID RAM, except for the SPA, SPA location, and the
checksum of the E-EDID block where the SPA is located.
The structure of the internal E-EDID image for Port B is shown in
Rev. A May 2012
man_edid_a_enable
Figure 52.
0x1FF
0x180
0x17F
0x100
0xFF
0x80
0x7F
0x00

Figure 52: Port A E-EDID Structure and Mapping

is set to 1, the ADV7850 E-EDID/Repeater controller calculates the six checksums of the E-EDID
man_edid_b_enable
to 1. The structure of the internal E-EDID that is accessible on
Block 3 Checksum
0x1FE
Block 2 Checksum
0x17E
Block 1 Checksum
0xFE
Block 0 Checksum
0x7E
C interface at the EDID Map I
2
to 1. The image of the internal E-EDID that is accessed on the
Figure 53.
147
ADV7850
C address 0xA0.
2
C address.
2