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ADV7511W
Analog Devices ADV7511W Manuals
Manuals and User Guides for Analog Devices ADV7511W. We have
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Analog Devices ADV7511W manual available for free PDF download: Hardware User's Manual
Analog Devices ADV7511W Hardware User's Manual (45 pages)
Low-Power HDMI 1.4a Transmitter
Brand:
Analog Devices
| Category:
Transmitter
| Size: 0 MB
Table of Contents
Revision History
2
Table of Contents
3
Section 1: Introduction
7
Scope and Organization
7
Links
7
Symbols
7
Format Standards
7
Overview
8
Hardware Features
8
Supported Input Formats
8
Supported Output Formats
8
Section 2: Reference Documents
9
ADI Documents
9
Industry Specifications
9
Figure 1 ADV7511W Functional Block Diagram
10
Section 3: Block Diagram
10
Table 1 Electrical Specifications
11
Section 4: Specifications
11
Figure 2 Timing for Video Data Interface
13
Figure 3 Timing for I2S Audio Interface
13
Table 2 Absolute Maximum Ratings
14
ESD Caution
15
Explanation of Test Levels
15
Figure 4 Timing for S/PDIF Audio Interface
14
Figure 5 64-Lead LQFP Configuration (Top View - Not to Scale)
16
Section 5: Pin and Package Information
16
Table 3 Complete Pinout List ADV7511W
17
Figure 6 64-Lead Low-Profile Quad Flat Pack [LQFP-SW64-2]
19
Mechanical Drawings and Outline Dimensions
19
Section 6: Functional Description
20
Input Connections
20
Unused Inputs
20
Video Data Capture Block
20
Video Input Connections
20
Table 4 Input ID Selection
20
Table 5 Normal RGB or Ycbcr 4:4:4 (24 Bits) with Separate Syncs; Input ID = 0
21
Table 6 Ycbcr 4:2:2 Formats (24, 20, or 16 Bits) Input Data Mapping: 0X48[4:3]='00' (Evenly Distributed) Input ID=1 or 2
22
Figure 7 2X Clock Timing
23
Table 7 Ycbcr 4:2:2 Formats (12, 10, or 8 Bits) Input Data Mapping: 0X48[4:3]='00' (Evenly Distributed) Input ID
23
Table 8 Ycbcr 4:2:2 (8 Bits) DDR with Separate Syncs: Input ID = 6, Right Justified (R0X48[4:3] = '01')
24
Table 9 Ycbcr 4:2:2 (8 Bits) DDR with Separate Syncs: Input ID = 6, Left Justified (R0X48[4:3] = '10')
24
Table 10 Ycbcr 4:2:2 (12, 10, 8 Bits) DDR with Separate Syncs:input ID = 6, Evenly Distributed (R0X48[4:3] = '00')
25
Audio Data Capture Block
26
Supported Audio Input Format and Implementation
26
Figure 8 DDR de Timing - Register 0X16[1] = 1
26
Figure 9 DDR de Timing - Register 0X16[1] = 0
26
Table 11 Audio Input Format Summary
27
Inter-IC Sound (I2S) Audio
28
Figure 10 I2S Standard Audio - Data Width 16 to 24 Bits Per Channel
28
Table 12 SCLK Duty Cycle
28
Figure 11 I2S Standard Audio - 16-Bit Samples Only
29
Figure 12 Serial Audio - Right-Justified
29
Figure 13 Serial Audio - Left-Justified
29
Sony/Philips Digital Interface (S/PDIF)
30
HBR Audio
30
Hot Plug Detect (HPD) Pin
30
Power down / I2C Address (PD/AD)
30
Figure 14 AES3 Direct Audio
30
Figure 15 S/PDIF Data Timing
30
Input Voltage Tolerance
31
Output Connections
31
Output Formats Supported
31
TMDS Outputs
31
ESD Protection
31
EMI Prevention
31
Display Data Channel (DDC) Pins
31
Interrupt Output (INT)
32
PLL Circuit
32
Consumer Electronic Control (CEC)
32
Unused Inputs
32
CEC Function
32
Figure 16 Typical All-HDMI Home Theatre
32
Video Data Formatting
33
Supported 3D Formats
33
DE, Hsync and Vsync Generation
33
Table 13 some Useful "End-User" CEC Features
33
Table 14 Supported 3D Formats
33
Color Space Conversion (CSC) Matrix
34
Figure 17 Sync Processing Block Diagram
34
Figure 18 Single Channel of CSC (In_A)
35
Table 15 Channel Assignment for Color Space Converter (CSC)
35
4:2:2 to 4:4:4 and 4:4:4 to 4:2:2 Conversion Block
36
DDC Controller
36
Inter-IC Communications (I2C)
36
Two-Wire Serial Control Port
36
Data Transfer Via I2C
37
Table 16 Serial Port Addresses
37
Serial Interface Read/Write Examples
38
Figure 19 Serial Port Read/Write Timing
38
Power Domains
39
Figure 20 Serial Interface-Typical Byte Transfer
39
Figure 21 Power Supply Domains
39
Power Consumption
40
Power Supply Sequencing
40
Table 17 Maximum Power Consumption by Circuit - Note These Values will Change after Characterization
40
Section 7: PCB Layout Recommendations
41
Power Supply Filtering
41
Figure 22 AVDD and PVDD Max Noise Vs. Frequency
41
Video Clock and Data Inputs
42
Audio Clock and Data Inputs
42
SDA and SCL
42
DDCSDA and DDCSCL
42
Figure 23 LC Filter Transfer Curve
42
Current Reference Pin: R_EXT
43
CEC Implementation
43
Figure 24 CEC External Connection
43
Figure 25 Example Schematic
44
Section 8: Glossary
45
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