N And Cts Parameters; Figure 132: Audio Clock Regeneration - Analog Devices ADV7850 Hardware Manual

the bit from 0 to 1 causes the one time synchronization, so setting the bit from 1 to 0 will have no effect.
The mapping between the I2S input signals to the Tx core and the HBR subpackets can be via the following controls:
• subpkt0_l_src
• subpkt0_r_src
• subpkt1_l_src
• subpkt1_r_src
• subpkt2_l_src
•
subpkt2_r_src
• subpkt3_l_src
•
subpkt3_r_src
Note: These fields are normally set to their respective default values. Since there is no standard for chip to chip HBR transfer, different
settings may be required to map the HBR stream input to a non ADI HDMI receiver device.
Refer to Table 93 for additional details on the HBR modes supported by the ADV7850.
papb_sync, Addr B8 (Main), Address 0x47[6]
For HBR audio this synchronizes the Pa and Pb syncwords with subpacket 0.
Function
papb_sync
0 <<
1

N and CTS Parameters

13.12.6
The audio data carried across the HDMI link to the downstream sink, which is driven by a TMDS clock only, does not retain the original
audio sample clock. The task of recreating this clock at the sink is called Audio Clock Regeneration (ACR). There are varieties of ACR
methods that can be implemented in an HDMI sink, each with a different set of performance characteristics. The HDMI specification
does not attempt to define exactly how these mechanisms operate. It does, however, present a possible configuration and define the data
items that the HDMI source shall supply to the HDMI sink in order to allow the HDMI sink to adequately regenerate the audio clock.
The HDMI specification also defines how that data shall be generated. In many video source devices, the audio and video clocks are
generated from a common clock (coherent clocks). In that situation, there exists a rational (integer divided by integer) relationship
between these two clocks. The ACR architecture can take advantage of this rational relationship and can also work in an environment
where there is no such relationship between these two clocks, that is, where the two clocks are truly asynchronous or where their
relationship is unknown.
f
128 ×
S
VIDEO CLOCK
N
Rev. A May 2012
Description
No function
Synchronize Pa and Pb syncwords with subpacket 0
SOURCE DEVICE
DIVIDE
CYCLE
BY
TIME
N
COUNTER
REGISTER
N
1
N AND CTS VALUES ARE TRANSMITTED USING THE "AUDIO CLOCK REGENERATION"
PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

Figure 132: Audio Clock Regeneration

SINK DEVICE
1
CTS
DIVIDE
TMDS
BY
CLOCK
CTS
1
N
370
ADV7850
MULTIPLY
f
128 ×
BY
S
N