Global Control Registers; Adv7850 Revision Identification; Power-Down Controls; Primary Power-Down Controls - Analog Devices ADV7850 Hardware Manual

3 GLOBAL CONTROL REGISTERS

The control bits described in this section deal with the general control of the chip and the three main sections of the ADV7850: the SDP,
the CP, and the HDMI receiver.

3.1 ADV7850 REVISION IDENTIFICATION

rd_info[15:0], IO, Address 0xE1[7:0]; Address 0xE2[7:0] (Read Only)
This readback displays the chip revision code.
Function
rd_info[15:0]
0x2101

3.2 POWER-DOWN CONTROLS

Primary Power-down Controls

3.2.1
power_down is the main power-down control. It is the main control for power-down for the HDMI Rx, SDP, VDP and CP sections
power_down, IO, Address 0x0C[5]
This control is used to enable power-down mode. This is the main I2C power-down control.
Function
power_down
0
1 
tx_power_down, Addr B8 (Main), Address 0x41[6]
Tx power down.
Function
tx_power_down
0
1 <<

Secondary Power-down Controls

3.2.2
The cp_pwrdn, xtal_pdn, core_pdn, and vdp_pdn controls allow various sections of the ADV7850 to be powered down.
For a power-sensitive application, it is possible to stop the clock to the CP to reduce power. cp_pwrdn enables this power-save mode. The
SDP, VDP, and HDMI blocks are not affected by this power-save mode. This allows the use of limited HDMI, SSPD, and STDI monitoring
features while reducing the power consumption. For full processing of HDMI input the CP core needs to be powered up.
xtal_pdn allows the user to power down the XTAL clock in the following sections:
• STDI blocks
•
SSPD blocks
• Free run synchronization generation block
• I C sequencer block, which is used for the configuration of the gain, clamp, and offset
2
• CP and HDMI sections
• Frequency measurement block, and its derivatives, for example, frequency settings for equalizers
Rev. A May 2012
Description
Version Number
Description
Chip operational
Enable chip power down
Description
Normal operation
HDMI Tx power down
29
ADV7850