Frame Synchronization (Frame Time Base Correction); Figure 46: Frame Synchronization Block Diagram - Analog Devices ADV7850 Hardware Manual

Function
sdp_v_pk_flip[2:0]
000
001
010
011
100 
101
110
111
6.15

FRAME SYNCHRONIZATION (FRAME TIME BASE CORRECTION)

The frame synchronizer block in the ADV7850 provides stable timing information and stable clock frequency in the event of irregularities
on the input signal. These irregularities include items such as VCR head switches, extra lines in a frame, too few lines in a frame, non
standard input frequency, or interrupted field sequence that occur during VCR trick mode inputs and during input channel changes.
Nominal 480i/576i H/V/F and/or CCIR-656 type timing and data is output from the system under all conditions.
block diagram for the system.
Input video is decoded in the decoder core to component YPrPb (or equivalent) with associated HSync, VSync, and field signals. The time
base correction (TBC) control block writes YPrPb data to the frame memories in the external SDRAM. The TBC control block
synthesizes H, V, and F timing signals with nominal 480i/576i timing and reads YUV data from the frame memories based on nominal
timing signals generated using a fixed frequency clock. This fixed frequency clock is also used to clock data out of the ADV7850. The
fixed frequency clock is user programmable but is intended to operate at 13.5 MHz, 27 MHz, or 54 MHz depending on the chosen output
format.
The external SDRAM memory is used to provide storage for fields of data.
The frame synchronization controls are described below.
sdp_fr_tbc_en, Addr 90 (SDP), Address 0x12[2]
This control is used to enable frame Time Based Correction (TBC).
Function
sdp_fr_tbc_en
1
0 
Rev. A May 2012
Description
64
128
256
512
1024
2048
3072
4095
YPbPr data
Video Data
Decoded H/V/F
and Decoded
H, V, F Timing
Core clk and dv
(Decoded from
Input)

Figure 46: Frame Synchronization Block Diagram

Description
Enable frame TBC
Disable frame TBC
YPbPr data
TBC
Nominal H/V/F
Control
External
DDR RAM
121
YPbPr data
Output Video
(H,V,F/CCIR56
Nominal Nominal H,V,F
Timing)
Fixed freq output clk
DDS Clock
Generator
2
(I C
programmable
fixed frequency)
ADV7850
Figure 46 provides a