Software Implementation - Analog Devices ADV7850 Hardware Manual

The BKVS interrupt bit bksv_flag_intr
when authentication is complete, the system should monitor
this time, the host controller should be used to compare the BKSV list read from the sink with the revocation list. Once the host controller
has verified none of the BKSVs read from the sink are revoked, the ADV7850 can be configured to send content down to the sink.
bksv_count[6:0], Addr B8 (Main), Address 0xC7[6:0] (Read Only)
This readback indicates the Bksvs available in the sink's Bksv FIFO.

Software Implementation

13.14.3
Figure 135 shows a block diagram of HDCP software implementation for all cases using the ADV7850 Tx HDCP/EDID controller state
machine. The diagram illustrates the necessary interactions with the ADV7850 registers and EDID memory, as well as when these
interactions should take place. Note that there is no need to interact with the DDC bus directly because all the DDC functionality is
controlled by the Tx HDCP/EDID controller and follows the HDCP specification 1.4.
Rev. A May 2012
KSV Number Field Name
bksv9_byte_2[7:0]
bksv9_byte_3[7:0]
bksv9_byte_4[7:0]
10 bksv10_byte_0[7:0]
bksv10_byte_1[7:0]
bksv10_byte_2[7:0]
bksv10_byte_3[7:0]
bksv10_byte_4[7:0]
11 bksv11_byte_0[7:0]
bksv11_byte_1[7:0]
bksv11_byte_2[7:0]
bksv11_byte_3[7:0]
bksv11_byte_4[7:0]
12 bksv12_byte_0[7:0]
bksv12_byte_1[7:0]
bksv12_byte_2[7:0]
bksv12_byte_3[7:0]
bksv12_byte_4[7:0]
set to 1 should be cleared by setting
hdcp_controller_state[3:0]
Register Addresses
0x2F[7:0] byte 2
0x30[7:0] byte 3
0x31[7:0] byte 4
0x32[7:0] byte 0
0x33[7:0] byte 1
0x34[7:0] byte 2
0x35[7:0] byte 3
0x36[7:0] byte 4
0x37[7:0] byte 0
0x38[7:0] byte 1
0x39[7:0] byte 2
0x3A[7:0] byte 3
0x3B[7:0] byte 4
0x3C[7:0] byte 0
0x3D[7:0] byte 1
0x3E[7:0] byte 2
0x3F[7:0] byte 3
0x40[7:0] byte 4
bksv_flag_intr to 1 after each set of BKSVs is read. To check
and wait until it reaches the value or state 4. At
385
ADV7850