Ddc And Vga Pins Power Down; Reset Controls And Global Pin Controls; Reset Pin; Reset Controls - Analog Devices ADV7850 Hardware Manual

Function
pdn_adc3
0
1 

DDC and VGA Pins Power Down

3.2.6
ddc_pwrdn[7:0], Addr 68 (HDMI), Address 0x73[7:0]
This control is used to power down the DDC pads.
Function
ddc_pwrdn[7:0]
0 
1
vga_pwrdn, Addr 68 (HDMI), Address 0x72[3]
This control is used to power down the VGA EDID pads.
Function
vga_pwrdn
0 
1

3.3 RESET CONTROLS AND GLOBAL PIN CONTROLS

Reset Pin

3.3.1
The ADV7850 can be reset by a low reset pulse on the RESET pin with a minimum width of 5 ms. It is recommended to wait 5 ms after
the low pulse before an I C write is performed to the ADV7850.
2

Reset Controls

3.3.2
main_reset, IO, Address 0xFF[7] (Self-Clearing)
This control is used to apply a main reset where I2C registers will be reset to their default values. This is a self clearing bit.
Function
main_reset
0 
1
vdp_reset, IO, Address 0xFF[5] (Self-Clearing)
This control is used to apply a VDP FIFO and a controller reset. This is a self clearing bit.
Function
vdp_reset
0 
1
sdp_reset, IO, Address 0xFF[3] (Self-Clearing)
This control is used to apply a SDP reset. This is a self clearing bit.
Rev. A May 2012
Description
Power up
Power down
Description
Power up DDC pads
Power down DDC pads
Description
Power up VGA EDID pads
Power down VGA EDID pads
Description
Normal operation
Apply main I2C reset
Description
Not reset
Apply VDP reset
33
ADV7850