Tmds Measurement; Tmds Measurement After Tmds Pll - Analog Devices ADV7850 Hardware Manual

Note: To enable the fast switching feature, the termination should be set manually for each port. When manual mode is enabled the
termination for each port is set individually by the clock_termx_disable control bits (where x is a, b, c or d).
clock_terma_disable, Addr 68 (HDMI), Address 0x83[0]
This control is used to disable clock termination on Port A. It can be used when term_auto is set to 0.
Function
clock_terma_disable
0
1 
clock_termb_disable, Addr 68 (HDMI), Address 0x83[1]
This control is used to disable clock termination on Port B. It can be used when term_auto is set to 0.
Function
clock_termb_disable
0
1 
clock_termc_disable, Addr 68 (HDMI), Address 0x83[2]
This control is used to disable clock termination on Port C. It can be used when term_auto is set to 0.
Function
clock_termc_disable
0
1 
clock_termd_disable, Addr 68 (HDMI), Address 0x83[3]
This control is used to disable clock termination on Port D. It can be used when term_auto is set to 0.
Function
clock_termd_disable
0
1 

7.17 TMDS MEASUREMENT

The ADV7850 contains logic that measures the frequency of the TMDS clock transmitted on the TMDS clock channel. The TMDS
frequency can be read back via the

TMDS Measurement After TMDS PLL

7.17.1
The TMDSFREQ measurement is provided by a clock measurement circuit located after the TMDS PLL. The TMDS PLL must, therefore,
be locked to the incoming TMDS clock in order for the tmdsfreq and tmdsfreq_frac registers to return a valid measurement. The TMDS
frequency can be obtained using
Notes:
• The TMDS PLL lock status can be monitored via tmds_pll_locked.
Rev. A May 2012
Description
Enable termination Port A
Disable termination Port A
Description
Enable termination Port B
Disable termination Port B
Description
Enable termination Port C
Disable termination Port C
Description
Enable termination Port D
Disable termination Port D
tmdsfreq[8:0] and tmdsfreq_frac[6:0]
Equation 3.
=
F
TMDS
Equation 3: TMDS Frequency in MHz (Measured After TMDS PLL)
registers.
tmdsfreq _ frac
+
tmdsfreq
128
Figure 54
155
shows the algorithm that can be implemented on
ADV7850