Analog Devices ADV7850 Hardware Manual page 327

Function
enable_vdp_data_over
_spi
0 <<
1
spi_slave_in_burst_mode, IO, Address 0x1E[5]
This is valid when SPI is in slave mode.
Function
spi_slave_in_burst_mo
de
0
vdp_spi_master_busy, IO, Address 0x1D[1] (Read Only)
This readback indicates the status of the SPI interface.
Function
vdp_spi_master_busy
0 
1
vdp_spi_slave_busy, IO, Address 0x1D[0] (Read Only)
This readback indicates the status of the SPI interface.
Function
vdp_spi_slave_busy
0 
1
clock_polarity, IO, Address 0xE4[1]
This control is used to adjust the clock polarity for the SPI interface (CPOL).
Function
clock_polarity
0 
1
clock_phase, IO, Address 0xE4[0]
This control is used to adjust the clock phase control for SPI.
Function
clock_phase
0 
1
vdp_data_packet_size[5:0], IO, Address 0x1C[5:0]
This control is used to tell the SPI master how many bits to transmit.
Rev. A May 2012
Description
VDP FIFO is not cleared by SPI logic
VDP FIFO fast registers are cleared when one byte read.
Description
single byte mode, 1 = burst mode
Description
Master idle
Master busy
Description
Slave idle
Slave busy
Description
Normal polarity
Inverted polarity
Description
Data captured on rising edge of SPI clock
Data captured on falling edge of SPI clock
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ADV7850