Video Fifo; Figure 55: Hdmi Video Fifo - Analog Devices ADV7850 Hardware Manual

Function
bg_deep_color_mode[1
:0]
00 
01
10
11

7.19 VIDEO FIFO

The ADV7850 contains a FIFO located between the incoming TMDS data and the CP core (refer to
HDMI link will be at 1X for non deep color mode (24 bits), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively).
Data unpacking and data rate reduction must be performed on the incoming HDMI data to provide the CP core with the correct data rate
and data bit width. The video FIFO is used to pass data safely across the clock domains.
The video FIFO also provides extreme robustness to jitter on the TMDS clock. The CP clock is generated by a DPLL running on the
incoming TMDS clock, and the CP clock may contain less jitter than the incoming TMDS clock. The video FIFO provides immunity to
the incoming jitter and the resultant clock phase mismatch between the CP clock and the TMDS clock.
T M D S
C l o c k
T M D S
C h a n n e l 0
T M D S
C h a n n e l 1
T M D S
C h a n n e l 2
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are
about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of
FIFO status and control registers.
dcfifo_level[2:0], Addr 68 (HDMI), Address 0x1C[2:0] (Read Only)
This readback indicates the distance between the read and write pointers. Overflow/underflow would read as level 0. Ideal centered
functionality would read as 0b100.
Function
dcfifo_level[2:0]
000 
001
010
011
100
101
110
111
Rev. A May 2012
Description
8-bit color per channel
10-bit color per channel
12-bit color per channel
16-bit color per channel
T M D S
+
-
P L L
T M D S C h 0
+
-
T M D S
S a m p l in g
T M D S C h 1
+
a n d
-
D a t a
R e c o v e r y
T M D S C h 2
+
-
Description
FIFO underflowed or overflowed
FIFO about to overflow
FIFO has some margin
FIFO has some margin
FIFO perfectly balanced
FIFO has some margin
FIFO has some margin
FIFO about to underflow
D i v i d e r
R
1 2
G
1 0
1 2
T M D S
B
D e c o d i n g
1 0
1 2
H S
V S
1 0
D E

Figure 55: HDMI Video FIFO

160
Figure 55). Data arriving over the
D P L L
R
1 2
G
1 2
B
F I F O
1 2
H S
V S
D E
ADV7850