Protocol For Main I C Port; Ddc Ports; I 2 C Protocols For Access To The Internal E-Edid; Figure 137: Bus Data Transfer - Analog Devices ADV7850 Hardware Manual

Protocol for Main I
14.1.2
The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL
remains high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the
next eight bits (7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the
transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other
devices withdraw from the bus at this point and maintain an idle condition.
In the idle condition, the device monitors the SDA and SCLK lines for the start condition and the correct transmitted address. The R/W
bit determines the direction of the data. A logic 0 on the LSB of the first byte means that the master will write information to the
peripheral. A logic 1 on the LSB of the first byte means that the master will read information from the peripheral.
Each of the ADV7850 maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the map address and the second byte as the starting subaddress. The subaddresses
auto increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers.
Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with
normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period the user should
issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress
is issued by the user, the ADV7850 does not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress in auto increment mode, the following actions are taken:
• In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse.
•
In write mode, the data for the invalid byte is not loaded into any subaddress register. A no acknowledge is issued by the
ADV7850 and the part returns to the idle condition.
14.2

DDC PORTS

Four I C ports, DDC port A, port B, port C and port D, allow an HDMI host to access the internal E-EDID and the HDCP registers. Note
2
that the DDC ports are 5 V tolerant, which simplifies the hardware between the HDMI connector and the ADV7850.
I C Protocols for Access to the Internal E-EDID
2
14.2.1
An I C master connected on a DDC port can access the internal E-EDID using the following protocol:
2
• Write sequence, as defined in Section
• Read sequence, as defined in Section
• Current address read sequence:
Allows the master on the DDC port to read access internal E-EDID without specifying the subaddress that must be read. The
Rev. A May 2012
C Port
2

Figure 137: Bus Data Transfer

Figure 138: Read and Write Sequence

14.1.2
14.1.2
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ADV7850