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Analog Devices ADV7850 Hardware Manual

Fast switching 4:1 hdmi 1.4 receiver with 3d-comb decoder and digitizer

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Fast Switching 4:1 HDMI 1.4 Receiver with 3D-Comb Decoder and Digitizer

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ADV7850

Fast Switching 4:1 HDMI 1.4 Receiver

With 3D-Comb Decoder and Digitizer

HARDWARE

MANUAL

Rev. A

May 2012

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Page 1 ADV7850 Fast Switching 4:1 HDMI 1.4 Receiver With 3D-Comb Decoder and Digitizer HARDWARE MANUAL Rev. A May 2012...
Page 2: Table Of Contents
ADV7850 TABLE OF CONTENTS INTRODUCTION TO ADV7850 HARDWARE MANUAL ....................11 ............................11 ESCRIPTION OF THE ARDWARE ANUAL .................................. 11 OPYRIGHT NFORMATION ......................................11 ISCLAIMER ............................11 RADEMARK AND ERVICE OTICE ................................... 11 UMBER OTATIONS ............................... 11 EGISTER CCESS ONVENTIONS ...............................
Page 3 ADV7850 ANALOG FRONT END ................................. 42 ADC S ..................................42 AMPLING LOCK ................................42 S AND OLTAGE LAMPS Analog Input Hardware Configuration ..........................42 5.2.1 Clamp Operation ................................43 5.2.2 SDP Clamp Operation ............................... 43 5.2.3 ..................................45 NALOG NPUT UXING Analog Input Routing Recommendation ..........................
Page 4 ADV7850 SDP G ..................................81 PERATION SDP Luma Gain ................................82 6.6.1 Chroma Gain ..................................84 6.6.2 Peak White Feature ................................85 6.6.3 Peak Chroma ..................................86 6.6.4 Color Kill.................................... 86 6.6.5 3D C ....................................... 87 3D Comb Activation ................................. 87 6.7.1...
Page 5 ADV7850 Manual Operation ..............................150 7.13.2 7.14 .................................... 151 ELECTION 7.15 ......................151 WITCHING AND ACKGROUND ELECTION 7.16 TMDS C ............................153 LOCK CTIVITY ETECTION Clock and Data Termination Control ........................154 7.16.1 7.17 TMDS M ................................. 155 EASUREMENT TMDS Measurement After TMDS PLL ........................155 7.17.1...
Page 6 ADV7850 Source Number and Channel Number ........................198 7.33.4 Sampling and Frequency Accuracy ..........................198 7.33.5 Word Length ................................199 7.33.6 Channel Status Copyright Value Assertion ....................... 199 7.33.7 Monitoring Change of Audio Sampling Frequency ....................200 7.33.8 7.34 ............................200...
Page 7 ADV7850 Manual Gain Control ..............................245 9.3.4 Manual Gain Filter Mode ............................... 247 9.3.5 Automatic Gain Control ..............................247 9.3.6 9.3.6.1 Readback Signals from AGC Block ............................249 CP O ....................................252 FFSET LOCK CP D ..............................253 ATH FOR NALOG Pregain Block ...................................
Page 8 SPI Data Formats – Master Mode ........................... 324 10.7.2 Configuring Master Mode on the SPI Port ........................ 326 10.7.3 SPI VDP Controls and Readbacks ..........................328 10.7.4 ADV7850 VDP Interrupt Generation ........................330 10.7.5 AUDIO CODEC ................................... 333 11.1 ................................333 AUDIO CODEC OVERVIEW 11.2...
Page 9 ADV7850 13.10 EDID/HDCP C ..........................355 ONTROLLER RROR ODES 13.11 ....................................356 IDEO ETUP Input Format ................................356 13.11.1 Video Mode Detection ..............................356 13.11.2 Pixel Repetition ................................357 13.11.3 Video Related Packets and InfoFrames ........................358 13.11.4 AVI InfoFrame ................................358 13.11.5...
Page 10 ATA AND LOCKS 16.5 ..................................... 431 IGITAL NPUTS 16.6 XTAL ..........................431 ALUE ELECTION APPENDIX B ..................................433 17.1 ADV7850 T ........................... 433 YPICAL ONNECTION IAGRAMS APPENDIX C ..................................440 18.1 ..............................440 ACKAGE UTLINE RAWING 18.2 ..................................440 RDERING UIDE APPENDIX D ..................................
Page 11: Introduction To Adv7850 Hardware Manual
Analog Devices, Inc. (ADI) reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Page 12 Direct Digital Frequency Synthesizer Data Enable Data Identification Word Delay Locked Loop Digital Noise Reduction Data Preprocessor Device Under Test (designate the ADV7850 unless stated otherwise) Digital Visual Interface End of Active Video Enhanced Definition Electromagnetic Compatibility Equalizer High Definition...
Page 13: Control Description
ADV7850 Acronym/Abbreviation Description Single Data Rate SHA-1 Refer to HDCP documentation. SMPTE Society of Motion Picture and Television Engineers Signal to Noise Ratio Sync on Green Sync on Y Source Physical Address Source Production Descriptor SSPD Synchronization Source Polarity Detector...
Page 14: References
ADV7850 1.9 REFERENCES • HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4, June 5, 2009 • Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006 • CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006 •...
Page 15: Introduction
Current and voltage clamp control loops ensure that any DC offsets are removed from the video signal. The clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. The ADV7850 can support two composite outputs for full SCART support.
Page 16: Standard Definition Processor
The ADV7850 implements a patented adaptive digital line length tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7850 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs).
Page 17: Audio Codec
C interface or ancillary data stream. 2.5 AUDIO CODEC The ADV7850 contains a 24-bit, 48 kHz stereo CODEC. The stereo audio ADC converts analog audio inputs and provides the data to the back end via the HDMI interface. The stereo audio DAC receives I S data from the back end and converts it to an analog audio output.
Page 18: Component Video Processing
ADV7850 • Color controls that include hue, brightness, saturation, and contrast Component Video Processing 2.6.4 • Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, and 1080p • Automatic adjustments for gain (contrast) and offset (brightness); manual adjustment controls are also supported •...
Page 19: Functional Block Diagram
ADV7850 2.7 FUNCTIONAL BLOCK DIAGRAM FASTSWITCHING BLOCK + HDMI DECODE + MUX PROGRAMMABLE DECIMATION FILTERS VIDEO OUTPUT FORMATTER AUDIO OUTPUT FORMATTER Figure 2: Functional Block Diagram Rev. A May 2012...
Page 20: Pin Description
TX_VDD33 SDVDD SDVDD LDQS DQ15 DQ13 AVIN1 AVIN2 AVIN4 AVIN5 Figure 3: ADV7850 Pin Configuration Table 1: Function Descriptions Pin No. Mnemonic Description Ground Ground Ground RXB_2+ Digital Input Channel 2 true of Port B in the HDMI interface. RXB_1+ Digital Input Channel 1 true of Port B in the HDMI interface.
Page 21 ADV7850 Pin No. Mnemonic Description ARC_C Single ended Audio Return Channel of Port C in the HDMI interface. Ground RXD_2+ Digital Input Channel 2 true of Port D in the HDMI interface. RXD_1+ Digital Input Channel 1 true of Port D in the HDMI interface.
Page 22 ADV7850 Pin No. Mnemonic Description RXD_5V 5V detect pin for Port D in the HDMI interface. VGA_5V 5V detect inout for VGA connector DDCA_SCL Serial clock for DDC bus of Port A. DDCA_SCL is 5 V tolerant. DDCA_SDA Serial data for DDC bus of Port A. DDCA_SDA is 5 V tolerant.
Page 23 ADV7850 Pin No. Mnemonic Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground FILTA Audio Codec ADC filter capacitor VREF_AUDIO Audio Codec block reference voltage capacitor EP_CSB External EDID EEPROM interface EP_SCK External EDID EEPROM interface...
Page 24 ADV7850 Pin No. Mnemonic Description Ground Ground Ground Ground Ground Ground Ground Ground Ground AC_AVDD Audio block supply (3.3V) AC_AVDD Audio block supply (3.3V) HPOUT_R Headphone output right channel HPOUT_L Headphone output left channel HA_AP4 HDMI Audio port output HA_AP3/INT3 HDMI Audio port output or External Interrupt pin 3.
Page 25 ADV7850 Pin No. Mnemonic Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground TTX_SCLK VBI data interface TTX_MOSI VBI data interface TTX_MISO VBI data interface TTX_CSB VBI data interface Video Digital supply (1.8V) Ground Ground Ground...
Page 26 ADV7850 Pin No. Mnemonic Description Video Digital supply (1.8V) Video Digital supply (1.8V) TEST2 Test pin, do not connect Ground Ground Ground AVIN13 Analog video mux input channel AVIN12 Analog video mux input channel AVIN11 Analog video mux input channel...
Page 27 ADV7850 Pin No. Mnemonic Description SDRAM block address signal SDRAM write enable signal AA10 Ground AA11 SDRAM data line AA12 SDRAM data line AA13 SDRAM data line AA14 DQ11 SDRAM data line AA15 UDQSN SDRAM upper data strobe compliment signal...
Page 28 ADV7850 Pin No. Mnemonic Description SDRAM interface Chip Select. SDRAM CS Enables and disables the command decoder on the RAM. One of four command signals to the external SDRAM. SDRAM interface Differential Clock Compliment Output. All address and control output signals to the RAM should be sampled on the positive edge of CK and on the negative edge of CKN.
Page 29: Global Control Registers
ADV7850 3 GLOBAL CONTROL REGISTERS The control bits described in this section deal with the general control of the chip and the three main sections of the ADV7850: the SDP, the CP, and the HDMI receiver. 3.1 ADV7850 REVISION IDENTIFICATION rd_info[15:0], IO, Address 0xE1[7:0];...
Page 30: Power-Down Mode
1  Power down VDP section Power-down Mode 3.2.3 The ADV7850 supports the following power-down modes. • In power-down mode 1, selected sections and pads are kept active to provide E-EDID and +5 V antiglitch filter functionality. Rev. A May 2012...
Page 31: Edid Support In Power-Off Mode
3.2.4 The ADV7850 fully supports EDID read functionality in a powered off configuration. The 5V signal from the HDMI or graphic cable can be used to power the EDID controller on the ADV7850. Onboard regulators will provide a 3.3V signal to power the SPI EEPROM.
Page 32: Adc Power-Down Control
Figure 4: Required Hardware Configuration When Using +5 V from HDMI Source(s) to Provide EDID Support in Powered Off State ADC Power-down Control 3.2.5 The ADV7850 contains 12-bit ADCs (ADC 0, ADC 1, ADC 2, and ADC3). It is possible to power down each ADC individually, if required. pdn_adc0, AFE, Address 0x00[0] This control is used to power down ADC0.
Page 33: Ddc And Vga Pins Power Down
Reset Pin 3.3.1 The ADV7850 can be reset by a low reset pulse on the RESET pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the low pulse before an I C write is performed to the ADV7850.
Page 34: Tristate Pins
HDMI mode, as the transmitter will have already authenticated the ADV7850 when the latter is switched into HDMI mode. Simultaneous mode is also used for SDP and HDMI audio mode (refer to Section 4.2.)
Page 35 Non simultaneous mode In this mode, the ADV7850 processes either analog or HDMI/DVI inputs. The HDMI section is disabled when the ADV7850 is configured to process analog inputs. The ADCs are powered down when the part is configured to process HDMI/DVI inputs in HDMI mode.
Page 36: Primary Mode And Video Standard
HDMI mode HDMI mode. In HDMI mode the ADV7850 can receive and decode HDMI or DVI data throughout the DVI/HDMI receiver front end. Video data from the HDMI receiver is routed to the HDMI Tx while audio data is available on the audio interface.
Page 37 ADV7850 prim_mode[3:0] vid_std[5:0] Code Description Processor Code Input Video Output Resolution Comment 00011 Reserved Reserved e.g. CVBS 00100 SD 2x1 720x480i/576i SCART RGB 00101 SD 4x1 720x480i/576i SCART RGB 00110 Reserved Reserved 00111 Reserved Reserved 01000 SD 2x1 720x480i/576i 01001...
Page 38 ADV7850 prim_mode[3:0] vid_std[5:0] Code Description Processor Code Input Video Output Resolution Comment 010110 HD 1x1 1250 1920 x 1080i SMPTE 295M 010111 HD 1x1 1250 1920 x 1152i 011000 Reserved Reserved 011001 HD 2x1 720p 1280 x 720p SMPTE 296M...
Page 39 ADV7850 prim_mode[3:0] vid_std[5:0] Code Description Processor Code Input Video Output Resolution Comment 000101 Reserved Reserved 000110 Reserved Reserved 000111 Reserved Reserved 001000 SD 2x1 YUV 720x480i/576i 001001 Reserved Reserved 001010 YPrPb SD 2x1 RGB 720x480i/576i Reserved Reserved Reserved 111111 Reserved...
Page 40: Setting The Vertical Frequency
Frame TBC and 3D comb are not available in this mode. When switching into this mode it is recommended to mute the audio as the changing modes may cause a disturbance to the audio output. To configure the ADV7850 for this mode, the following I writes should be carried out: Rev.
Page 41: Primary Mode And Video Standard Configuration For Hdmi Free Run
4.3 PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN To support Free run in HDMI Mode, the ADV7850 must use the CP core. Free Run is only supported up to 225MHz. If free run is enabled in HDMI mode, PRIM_MODE [3:0] and VID_STD [5:0] should be used to specify the output resolution to which the ADV7850 free runs.
Page 42: Analog Front End
• Eight trilevel input detection blocks 5.1 ADC SAMPLING CLOCK The ADV7850 has two main modes of operation for sampling the input analog video: CP mode and SDP mode. This is determined by the primary mode setting. • When the SDP is enabled, fixed 108 MHz sampling is applied to the ADCs. The SDP processes the video signal and, using a line length tracking processor, resamples the incoming video so that 720 active pixels are always generated per line.
Page 43: Clamp Operation
5.2.2 The ADV7850 has a clamp in front of each of its ADCs. The purpose of the clamp is to ensure that the video input signal lies inside the range of the ADC. In component and graphics modes, voltage clamps are used; and in standard definition modes, current clamps are used.
Page 44: Figure 8: Sdp Clamping Overview
ADV7850 Figure 8: SDP Clamping Overview The clamping can be divided into two sections: • Clamping before the ADC (analog domain): digitally controlled current sources • Clamping after the ADC (digital domain): digital processing block The ADCs can digitize an input signal if it resides within the ADC input voltage range of 1.0 V. An input signal with a DC level that is too large or too small will be clipped at the top or bottom of the ADC range.
Page 45: Analog Input Muxing
5.3 ANALOG INPUT MUXING The ADV7850 has thirteen analog input pins, Ain1 to Ain13. The user must select the Ain pin signals routed to the ADC in order to process the video signals that appear on the analog inputs. The ADV7850 has an integrated analog muxing section to route the video signals to the ADCs.
Page 46: Automatic Input Muxing Selection
Note that CVBS, YC and SD components have to be manually routed using adc0_sw_man[3:0], adc1_sw_man[3:0], adc2_sw_man[3:0], adc3_sw_man[3:0] while adc_switch_man is set to 1. (Refer to Section 5.5.1.) Figure 10: ADV7850 Input Functional Diagram ain_sel[2:0], AFE, Address 0x02[2:0] This control is used to select the analog input muxing mode. Rev. A May 2012...
Page 47: Manual Input Muxing Overview
5.5 MANUAL INPUT MUXING OVERVIEW By accessing a set of manual override muxing registers, the analog input muxes of the ADV7850 can be controlled directly. This is referred to as manual input muxing (refer to Section 5.5.1).
Page 48: Table 4: Manual Input Muxing
ADV7850 adc0_sw_man[3:0], AFE, Address 0x03[7:4] This control is used to manually route analog inputs to ADC0. Function adc0_sw_man[3:0] Description 0101 Ain5 1010 Ain10 1011 Ain11 1100 Ain12 1101 Ain13 All others Reserved adc1_sw_man[3:0], AFE, Address 0x03[3:0] This control is used to manually route analog inputs to ADC 1.
Page 49: Video Output Mux
ADV7850 adc0_sw_man[3:0] adc1_sw_man[3:0] ADC0 ADC1 ADC2 ADC3 adc2_sw_man[3:0] Connected to Connected to Connected to Connected to adc3_sw_man[3:0] 0101 AIN5 AIN5 0110 AIN6 0111 AIN7 1000 AIN8 1001 AIN9 1010 AIN10 1011 AIN11 AIN11 AIN11 AIN11 1100 AIN12 1101 AIN13 1110...
Page 50: Sync1-3 Input Control
As shown in Figure 11, the ADV7850 has three input synchronization control pins: SYNC1, SYNC2 and SYNC3. These pins are used for signals with embedded synchronization, for example, SOG or SOY type signals. SOG is associated with RGB input video; SOY is associated with component YPrPb input video.
Page 51: Automatic Synchronization Configuration
ADV7850 Figure 11: Synchronization Stripper Circuit Automatic Synchronization Configuration 5.7.1 In addition to configuring the analog input muxes, ain_sel[2:0]controls automatically the associated synchronization channel routing. Refer to Figure 9 and the ain_sel[2:0] description for the routing details when ain_sel[2:0] is programmed.
Page 52: Synchronization Slicers
Reserved 5.8 SYNCHRONIZATION SLICERS The ADV7850 has two synchronization slicer blocks, which are placed before the synchronization processing sections, as shown in Figure The purpose of a synchronization slicer is to provide a reliable synchronization signal to the STDI and SSPD circuits in the component processor so that a robust identification of standard is made.
Page 53: Sync Stripper Slice Level
10, the voltage levels to be sliced exceed the power supplies of the ADV7850 and, therefore, are beyond the range of the ADV7850 TRI inputs. The applied signals need to be reduced to fit in the range of the slicers. This is done by utilizing resistor divider networks at the inputs to TRI1-8.
Page 54: Trilevel Input Controls
Figure 12: D-Terminal Resistor Dividers Trilevel Input Controls 5.8.5 The ADV7850 has eight trilevel slicers, as shown in Figure 13. Each trilevel slicer is capable of operating in two modes. The first mode is bilevel mode where the input signal can be sliced at a single voltage level to determine the voltage level (refer to Table 8).
Page 55 ADV7850 tri1_slicer_pwrdn, AFE, Address 0x1D[6] This control is used to power down the Tri1 slicer. Function tri1_slicer_pwrdn Description Power up 1  Power down tri2_slicer_pwrdn, AFE, Address 0x1E[6] This control is used to power down the Tri2 slicer. Function tri2_slicer_pwrdn...
Page 56: Bilevel/Trilevel Selection
ADV7850 tri7_slicer_pwrdn, AFE, Address 0x23[6] This control is used to power down the Tri7 slicer. Function tri7_slicer_pwrdn Description Power up 1  Power down tri8_slicer_pwrdn, AFE, Address 0x24[6] This control is used to power down the Tri8 slicer. Function tri8_slicer_pwrdn...
Page 57: Trilevel Slicer Readbacks
ADV7850 Function tri4_bilevel_slice_en Description Bilevel slicing 1  Trilevel slicing tri5_bilevel_slice_en, AFE, Address 0x21[5] This control is used to enable bilevel slicing on the Tri5 input. Function tri5_bilevel_slice_en Description Bilevel slicing 1  Trilevel slicing tri6_bilevel_slice_en, AFE, Address 0x22[5] This control is used to enable bilevel slicing on the Tri6 input.
Page 58 ADV7850 Function tri1_readback[1:0] Description Signal higher than upper level Signal lower than upper level Signal higher than lower level Signal lower than lower level tri2_readback[1:0], AFE, Address 0x27[5:4] (Read Only) This readback displays Tri2 DC levels. Function tri2_readback[1:0] Description Signal higher than upper level...
Page 59: Programming Trilevel Slicers
ADV7850 Function tri6_readback[1:0] Description Signal higher than upper level Signal lower than upper level Signal higher than lower level Signal lower than lower level tri7_readback[1:0], AFE, Address 0x28[3:2] (Read Only) This readback displays Tri7 DC levels. Function tri7_readback[1:0] Description Signal higher than upper level...
Page 60 ADV7850 Function tri2_upper_slice_level[2 Description 75 mV 225 mV 37 mV 011  525 mV 675 mV 825 mV 975 mV 1.125 V tri3_upper_slice_level[2:0], AFE, Address 0x1F[4:2] This control is used to set the upper slice level on the Tri3 input.
Page 61 ADV7850 Function tri5_upper_slice_level[2 Description 75 mV 225 mV 375 mV 011  525 mV 675 mV 825 mV 975 mV 1.125 V tri6_upper_slice_level[2:0], AFE, Address 0x22[4:2] This control is used to set the upper slice level on the Tri6 input.
Page 62: Lower Slice Levels
ADV7850 Function tri8_upper_slice_level[2 Description 75 mV 225 mV 375 mV 011  525 mV 675 mV 825 mV 975 mV 1.125 V 5.8.9.2 Lower Slice Levels tri1_lower_slice_level[1:0], AFE, Address 0x1D[1:0] This control is used to set the lower slice level on the Tri1 input.
Page 63 This control is used to set the lower slice level on the Tri8 input. Function tri8_lower_slice_level[1 Description 75 mV 01  225 mV 375 mV 525 mV The ADV7850 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and Rev. A May 2012...
Page 64: Fast Blanking Configuration
(The trilevel input is selected using fb_select[3:0].) By default, the ADV7850 operates in a dynamic switching mode in which the source selection is under the control of the fast blank signal. This enables dynamic multiplexing between the CVBS and RGB sources. When the fast blank signal is logic HI, the RGB source is selected;...
Page 65: Scart Source Selection Control
1/8 of an ADC clock cycle. Increasing the value is equivalent to adding delay to the SCART fast blank signal. The reset value is chosen to give equalized channels when the ADV7850 internal anti aliasing filters are enabled and there is no unintentional delay on the PCB.
Page 66: Anti Aliasing Filters
Description 5.9.1 The ADV7850 has optional anti aliasing filters on each of the input channels. The filters are designed for SD, ED, and HD video with various bandwidths selectable via I C. These filters are most effective when ADC oversampling is selected.
Page 67 ADV7850 aa_filter_en1, AFE, Address 0x05[1] This control is used to enable the anti-aliasing filter on ADC1. Function aa_filter_en1 Description 0  Disable Enable aa_filter_en0, AFE, Address 0x05[0] This control is used to enable the anti-aliasing filter on ADC0. Function aa_filter_en0 Description 0 ...
Page 68: Figure 15: Response Of Anti Aliasing Filters
ADV7850 Table 9: Anti Alias Filter Frequency Characteristics aa_filt_high_bw[1:0] aa_filt_prog_bw[1:0] Fc (MHz) Frequency Response No –10 1000 Frequency (MHz) Figure 15: Response of Anti Aliasing Filters Rev. A May 2012...
Page 69: Standard Definition Processor
This block employs a color subcarrier recovery unit to regenerate the color subcarrier for any modulated chroma scheme. • Horizontal peaking/vertical peaking Horizontal and vertical luma peaking enhance the picture produced by the ADV7850. The luma peaking function operates to boost or attenuate the mid to high frequency component of the Y signal. •...
Page 70: Sdp General Setup
ADV7850 per line are output by the SDP. The ADV7850 uses a VSync and HSync PLL to provide an accurate and reliable lock for both perfect and imperfect video sources. • VSync PLL: provides extra filtering of the detected VSyncs to give improved vertical lock.
Page 71 ADV7850 Function sdp_ad_n443_en Description Enable NTSC-443 to be detected 0  Do not enable NTSC-443 to be detected sdp_ad_pal60_en, Addr 90 (SDP), Address 0x00[4] This control is used to enable autodetection of the PAL-60 standard. Setting this bit to 1 enables the corresponding standard to be detected.
Page 72: Pedestal Configuration In Sdp Modes
ADV7850 Function sdp_ad_pal_en Description Enable PAL-BGHID to be detected 0  Do not enable PAL-BGHID to be detected Pedestal Configuration in SDP Modes 6.3.2 The following controls dictate which standards the SDP core expects to have a pedestal. Standards that are expected to have a pedestal are clamped to the back porch level.
Page 73: Sdp Status Registers
ADV7850 Function sdp_palcn_ped_en Description Assume PAL-CombN inputs have a pedestal 0  Assume PAL-CombN inputs do not have a pedestal sdp_palm_ped_en, Addr 90 (SDP), Address 0x01[2] This control is used to force the part to assume that the corresponding standard has a pedestal. Standards with a pedestal are clamped to the pedestal level;...
Page 74: Input Status
ADV7850 Function sdp_video_detected Description Indicates valid SD/PR video input detected 0  Input invalid or no input connected sdp_c_chan_active, Addr 90 (SDP), Address 0x54[5] (Read Only) This readback displays the result of the CVBS/YC detection feature. Function sdp_c_chan_active Description Y/C input detected 0 ...
Page 75 ADV7850 sdp_frm_nstd, Addr 90 (SDP), Address 0x56[4] (Read Only) This readback indicates if the frame length in clock cycles is within the threshold set by sdp_frm_nstd_thr. Function sdp_frm_nstd Description Frame length in clock cycles not within +- sdp_frm_nstd_thr of nominal value 0 ...
Page 76 ADV7850 sdp_vs_std_mode, Addr 90 (SDP), Address 0x57[6] (Read Only) This readback indicates the detection of regular frame lengths on the input. Function sdp_vs_std_mode Description Regular frame lengths detected on input 0  Regular frame lengths not detected on input sdp_allow_3d_comb, Addr 90 (SDP), Address 0x57[4] (Read Only) This readback indicates the suitability of the input for 3D combing.
Page 77: Macrovision Status
ADV7850 sdp_pal_sw_locked, Addr 90 (SDP), Address 0x59[2] (Read Only) This readback indicates the detection of a PAL swinging burst sequence on the input. Function sdp_pal_sw_locked Description PAL swinging burst sequence detected 0  PAL swinging burst sequence not detected sdp_fsc_freq_ok, Addr 90 (SDP), Address 0x59[1] (Read Only) This readback indicates the status of the subcarrier frequency detected on the input if it is close to that of the selected standard, 3.58...
Page 78: Synctip Noise Measurement, Noisy And Very Noisy Signal Detection
ADV7850 sdp_mvcs_type3, Addr 90 (SDP), Address 0x50[1] (Read Only) This readback displays the detection of a Macrovision type 3 color stripe process. Function sdp_mvcs_type3 Description Macrovision type 3 color stripe process detected, only valid if sdp_mvcs_detect = 1 0 ...
Page 79: Additional Sdp Status Registers
Additional SDP Status Registers 6.4.6 An indication of signal strength can be obtained by reading back the burst power of the signal. The ADV7850 allows for two burst power measurements burst_power_act[11:0], Addr 94 (SDP_IO), Address 0x44[3:0]; Address 0x45[7:0] (Read Only) This readback displays the active path burst power measurement.
Page 80: Sdp Color Controls
The following registers provide user control over the picture appearance. They are independent of any other controls. For instance, the brightness control is independent of the picture clamping, although both controls affect the DC level of the signal. The ADV7850 provides 10-bit control of contrast, brightness, saturation, and hue.
Page 81: Contrast
0x000  0° 0x200 -180° 6.6 SDP GAIN OPERATION The SDP gain control within the ADV7850 is done on a purely digital basis. SDP gain correction takes place after digitization in the form of a digital multiplier. Rev. A May 2012...
Page 82: Sdp Luma Gain
Figure 17, the ADV7850 can decode a video signal as long as it fits into the ADC window. There are two components; the amplitude of the input signal, and the DC level on which it resides. The DC level is set by the clamping circuitry.
Page 83 1024 Equation 1: SDP Luma Gain Formula The luma gain range is from 0.5 to 4.0. Example: To program the ADV7850 into manual fixed gain mode with a desired gain of 0.95: • Equation 1 to convert the gain: 0.95 * 1024 = 972.8 •...
Page 84: Chroma Gain
1024 Equation 2: SDP Chroma Gain Formula The chroma gain range is from 0.5 to 8.0. Example: To program the ADV7850 into manual fixed chroma gain with a desired gain of 0.70 (signal): • Equation 2 to convert the gain: 0.70 * 1024 = 716.8...
Page 85: Peak White Feature
ADV7850 Function sdp_limit_c_gain Description Limit chroma gain to range of 50% to 200% 0  Normal operation sdp_limit_uv_gain, Addr 90 (SDP), Address 0x89[5] This control is used to limit U/V gain. Function sdp_limit_uv_gain Description Limit U/V gain to range of 50% to 200% 0 ...
Page 86: Peak Chroma
ADV7850 Function sdp_pw_rec_rate[11:0] Description 0x0F[3:0] sdp_pw_rec_rate[12:8] 0x10[7:0] sdp_pw_rec_rate[7:0] Peak Chroma 6.6.4 sdp_pc_en, Addr 90 (SDP), Address 0x05[6] This control is used to enable the peak-color chroma gain feature. Peak-color chroma overrides and reduces the gain of the chroma AGC if the chroma signal path becomes larger than a set threshold. Peak chroma can only act to reduce the AGC gain. When there are no more violations of the peak white threshold, the peak chrome algorithm allows the chroma AGC to restore the gain (based on the synchronization depth).
Page 87: Comb
Figure 18: 3D Comb and Motion Detection Operation When the picture content is static, the 3D comb filter in the ADV7850 combines video frames to give perfect Y/C separation results. Artifacts of 1D and 2D methods such as dot crawl, cross color, and hanging dots are eliminated. The sharpness and stillness of the decoded picture are improved using the 3D comb.
Page 88 The ADV7850 characterizes the signal as a clean, noisy, or very noisy input signal, and assesses whether or not the input signal has the following characteristics: • Incorrect number of lines •...
Page 89 ADV7850 sdp_ckill_dis_2d, Addr 90 (SDP), Address 0xA4[7] This control is used to enable 2D combing even if color kill mode is active. This would effectively be passthrough mode. Function sdp_ckill_dis_2d Description 1  Disable 2D comb if color kill active...
Page 90 ADV7850 Function sdp_noisy_fld_dis_3d Description 1  Disable 3D comb if noisy input detected and sdp_fld_nstd detected Allow 3D comb if noisy input detected even if sdp_fld_nstd detected sdp_noisy_frm_dis_3d, Addr 90 (SDP), Address 0xA4[1] This control is used to enable 3D combing if a noisy input is detected and a nonstandard frame length is detected.
Page 91 ADV7850 Function sdp_vnoisy_hsw1_dis_3 Description 1  Disable 3D comb if very noisy input detected and head switch detection algorithm 1 detects head switches Allow 3D comb if very noisy input detected even if head switch detection algorithm 1 detects head switches sdp_vnoisy_lc_dis_3d, Addr 90 (SDP), Address 0xA5[4] This control is used to enable 3D combing if a very noisy input is detected and an incorrect frame length is detected on the input.
Page 92: Comb Sensitivity
ADV7850 3D Comb Sensitivity 6.7.2 sdp_3d_comb_luma_sns[3:0], Addr 90 (SDP), Address 0xAA[3:0] This control is used to set the 3D comb luma sensitivity. Larger values increase 3D comb motion detection sensitivity to luma motion and noise. This is an unsigned control.
Page 93 The ADV7850 contains 33 different Y shaping filters available for selection using a 6-bit selection value. Four selection registers are provided so that different Y shaping filter can be selected for the VBI region, high quality inputs, low quality inputs, and SECAM inputs.
Page 94: Figure 19: Y Shaping Filter Flowchart
ADV7850 START VBI region In VBI region Use y_shape_sel_vbi Manual Selection y_shape_sel_auto_en SECAM CVBS Automatic Selection SECAM CVBS Not SECAM CVBS Use y_shape_sel_scm Use y_shape_sel_hqi CVBS Color Kill on Y/C and Color Kill on and force_ckill_hqi and force_ckill_hqi Possible B&W signal Possible B&W signal...
Page 95: Table 10: Y Shaping Filter Selection
ADV7850 Table 10: Y Shaping Filter Selection Y Shape Response Filter Type Comment General purpose low-pass luma shaping filter 1 FIR, linear Narrowest GPLPF General purpose low-pass luma shaping filter 2 FIR, linear General purpose low-pass luma shaping filter 3...
Page 96 ADV7850 Function sdp_hqi_req_std Description 1  HQI requires both stable and standard (nominal) timebase HQI requires only stable timebase sdp_force_comp_hqi, Addr 90 (SDP), Address 0x19[6] This control is used to force the use of a HQI Y shaping filter when a component input is applied. When this bit is disabled, the autoselection of the Y shaping filter is employed.
Page 97: Figure 20: Y Shaping Filter Selection From No. 0 To No. 13 In Table 10
ADV7850 Function sdp_y_shape_sel_scm[5 Description 011110  Default shape_1d_auto, Addr 90 (SDP), Address 0x96[7] This control is used to enable a 1D shaping filter when a nonstandard line frequency input is detected. Function shape_1d_auto Description Disable auto-1D shape filter selection 1 ...
Page 98: Figure 21: Y Shaping Filter Selection From No. 14 To 20 In Table 10
ADV7850 Figure 21: Y Shaping Filter Selection from No. 14 to 20 in Table 10 Figure 22: Y Shaping Filter Selection from No. 21 to 24 in Table 10 Rev. A May 2012...
Page 99: Figure 23: Y Shaping Filter Selection From No. 25 To 27 In Table 10
ADV7850 Figure 23: Y Shaping Filter Selection from No. 25 to 27 in Table 10 Figure 24: Y Shaping Filter Selection from No. 28 to 30 in Table 10 Rev. A May 2012...
Page 100: Figure 25: Y Shaping Filter Selection From No. 31 In Table 10
ADV7850 Figure 25: Y Shaping Filter Selection from No. 31 in Table 10 Rev. A May 2012...
Page 101: Input Shaping Filter Enables
ADV7850 Input Shaping Filter Enables 6.8.1 Refer to Section 6.4.5 for synctip noise measurement, noisy, and very noisy signal detection information. hqi_shaping_filter_disable, SDP Map, Address 0x98, [7:0] Function hqi_shaping_filte Bit Name Description r_disable[7:0] sdp_vnsy_dis_sfs_std Allows high quality input shaping filter even if a very noisy input is...
Page 102 ADV7850 Function sdp_fld_sfs_std Description 1  Disable HQI shape filter if clean input and sdp_fld_nstd detected Allow HQI shape filter even if sdp_fld_nstd detected sdp_blk_dis_sfs_std, Addr 90 (SDP), Address 0x98[3] This control is used to enable an HQI shaping filter when a nonstandard block length is detected.
Page 103: Chroma Shaping Filter
The ADV7850 contains 20 different C shaping filters that are available for selection using a 5-bit selection value. Three selection registers are provided so that different C shaping filters can be selected for high quality inputs, low quality inputs, and SECAM inputs.
Page 104: Figure 26: C Shaping Filter Flowchart
ADV7850 START Manual Selection sdp_c_shape_auto_en SECAM CVBS Automatic Selection Not SECAM CVBS SECAM CVBS Use sdp_c_shape_sel_scm[4:0] Use sdp_c_shape_sel_hqi[4:0] Component and S-Video Composite Video CVBS High quality input or SECAM sdp_force_comp_hqi Low quality component SECAM CVBS Use sdp_c_shape_sel_lqi[4:0] Use sdp_c_shape_sel_scm[4:0] sdp_csh_wbw_auto*...
Page 105: Table 11: C Shaping Filter Selection
ADV7850 Table 11: C Shaping Filter Selection C Shape Response Filter Type Comment CVBS-only narrow-band low-pass chroma shaping filter 1 FIR, linear Narrowest CVBS-only LPF CVBS-only narrow-band low-pass chroma shaping filter 2 FIR, linear CVBS-only narrow-band low-pass chroma shaping filter 3...
Page 106: Figure 27: C Shaping Filter Selection No. 0 To 3 In Table 11
ADV7850 sdp_c_shape_sel_lqi[4:0], Addr 90 (SDP), Address 0x1D[4:0] This control is used to allow selection of the C shaping filter for low quality inputs (LQI). Function sdp_c_shape_sel_lqi[4: Description 00010  Default sdp_c_shape_sel_scm[4:0], Addr 90 (SDP), Address 0x1E[4:0] This control is used to allow selection of the C shaping filter for SECAM input signals.
Page 107: Split Filter Selection
SPLIT FILTER SELECTION The ADV7850 offers a dynamic, pixel-by-pixel split filter alpha blending between a fixed, wide split filter and the split filter selected in the split filter selection register. The alpha blending determines if the region being combed would benefit most from a wide or a narrow split filter.
Page 108: If Filter Compensation
11xxx Reserved 6.11 IF FILTER COMPENSATION The ADV7850 offers ten different chroma path filters; four band-pass and six IF compensation, as detailed on Figure 31 Figure sdp_if_filt_sel[4:0], Addr 90 (SDP), Address 0x20[4:0] This control is used to compensate for SAW filter characteristics on a composite input as would be observed on a tuner output.
Page 109: Luma Transient Improvement And Chroma Transient Improvement
LUMA TRANSIENT IMPROVEMENT AND CHROMA TRANSIENT IMPROVEMENT The Luma Transient Improvement (LTI)/Chroma Transient Improvement (CTI) block enhances the picture produced in the ADV7850. The LTI/CTI block improves the steepness of the transitions. It uses adaptive peaking and non linear methods to provide enhancements without increasing noise or artifacts.
Page 110: Figure 33: Lti/Cti Operation Diagram
ADV7850 LTI/CTI Figure 33: LTI/CTI Operation Diagram sdp_lti_en, Addr 90 (SDP), Address 0x0E[1] This control is used to enable Luma Transient Improvement (LTI). Function sdp_lti_en Description Enable LTI 0  Disable LTI sdp_cti_en, Addr 90 (SDP), Address 0x0E[0] This control is used to enable Chroma Transient Improvement (CTI).
Page 111: Figure 34: Secam Signal Distortion
ADV7850 Clipping LF-Emphasis DE-Emphasis Filter Filter Dr Line Db Line DE-Emphasis Filter Slow tranisition Slow tranisition Figure 34: SECAM Signal Distortion SECAM CTI block is designed to improve this distortion, by making transitions steeper. The amount of improvement can be selected by sdp_scm_cti_gain[1:0].
Page 112: Figure 36: Lti Filter Response 1
ADV7850 Figure 36: LTI Filter Response 1 sdp_lti_level[6:0], Addr 90 (SDP), Address 0x25[6:0] This control is used to set the amount of LTI applied. A larger value corresponds to the sharpening of luma transients. Function sdp_lti_level[6:0] Description Bigger values More sharpening of luma transients 0 ...
Page 113: Figure 37: Cti Filter Response 0
ADV7850 Figure 37: CTI Filter Response 0 Figure 38: CTI Filter Response 1 sdp_lti_filt_sel, Addr 90 (SDP), Address 0x25[7] This control is used to select one of two filter responses available in LTI operation. Function sdp_lti_filt_sel Description Select filter response 1 as part of LTI 0 ...
Page 114: Ringing Reduction
4096 6.13 RINGING REDUCTION The ADV7850 incorporates a ringing reduction block. This block is used to reduce ringing artifacts that can appear around sharp edges. There are two controls to use a ringing reduction block. sdp_ring_red_en enables a block, and...
Page 115: Horizontal And Vertical Peaking
6.14 HORIZONTAL AND VERTICAL PEAKING The ADV7850 offers horizontal and vertical luma peaking to enhance the picture produced by the decoder. The luma peaking function operates to boost or attenuate the mid to high frequency component of the Y signal.
Page 116: Figure 40: Core Threshold In Horizontal Peaking
ADV7850 Enhancing Output Core Threshold Filtered Input Core Threshold Figure 40: Core Threshold in Horizontal Peaking sdp_h_pk_en, Addr 90 (SDP), Address 0x0E[2] This control is used to enable the horizontal peaking filter. This is a universal peaking control applied after 2D/3D mixing. It is applied whether or not 3D has been enabled.
Page 117: Figure 41: Horizontal Peaking High-Pass Filter
ADV7850 Function sdp_h_pk_band[1:0] Description 0  No filtering Highpass Bandpass peaking Alternative bandpass peaking Figure 41: Horizontal Peaking High-Pass Filter Figure 42: Horizontal Peaking Band-Pass Filter 1 Rev. A May 2012...
Page 118: Figure 43: Horizontal Peaking Band-Pass Filter 2
ADV7850 Figure 43: Horizontal Peaking Band-Pass Filter 2 sdp_h_pk_core[2:0], Addr 90 (SDP), Address 0x22[2:0] This control is used to select the horizontal threshold from the eight possible values listed in the following table. If the filtered output is less than the coring threshold, no high frequency is added back to the input. If the filter output is greater than the core threshold, it is passed through unchanged to the next stage.
Page 119: Figure 44: Peaking Controls
ADV7850 sdp_v_pk_flip[2:0] with sdp_v_pk_clip[1:0] are used to set the maximum amount of enhancement that can be added before the gain is applied. sdp_v_pk_flip[2:0] sets the maximum amount of enhancement. Above this value, the amount of enhancement is reduced. sdp_v_pk_clip[1:0] is a control that is applied after sdp_v_pk_flip[2:0]. It sets the positive and negative values of saturation. This...
Page 120: Figure 45: Vertical Peaking Filter
ADV7850 The vertical peaking filter response is shown in Figure Figure 45: Vertical Peaking Filter sdp_v_pk_core[2:0], Addr 90 (SDP), Address 0x23[2:0] This control is used to set the coring threshold for a vertical filter. Signals in the output of the filter that are below this level are cored to...
Page 121: Frame Synchronization (Frame Time Base Correction)
H, V, and F timing signals with nominal 480i/576i timing and reads YUV data from the frame memories based on nominal timing signals generated using a fixed frequency clock. This fixed frequency clock is also used to clock data out of the ADV7850. The fixed frequency clock is user programmable but is intended to operate at 13.5 MHz, 27 MHz, or 54 MHz depending on the chosen output...
Page 122: Free Run Mode
Free Run mode controls default color insertion and causes ADV7850 to generate a default clock. The state in which this happens can be monitored via the sdp_free_run readback. The default color of Free Run mode can be set by the following registers: •...
Page 123: Letterbox Detection
ADV7850 Function sdp_free_run_man_col_ Description 1  If in free run, output manual luma and chroma values set by sdp_free_run_y, sdp_free_run_v, and sdp_free_run_u If in free run, output decoded video data sdp_free_run_cbar_en, Addr 90 (SDP), Address 0xDD[1] This control is used to select the color bar pattern to be output in manual free run mode.
Page 124: Detection At Start Of Field
6.17.1 The ADV7850 expects a section of at least six consecutive black lines of video at the top of a field. Once those lines are detected, sdp_lbox_blk_top[7:0] reports back the number of black lines actually found. By default, the ADV7850 starts looking for those black lines in synchronization with the beginning of active video, for example, straight after the last VBI video line.
Page 125: Sdp Synchronization Output Signals
ADV7850 sdp_lbox_beg_del[3:0], Addr 90 (SDP), Address 0xDB[3:0] This control is used to set the letterbox detection begin line versus the default position. Function sdp_lbox_beg_del[3:0] Description 1000  Letterbox detection aligned with start line of active video. Window starts after VBI data line.
Page 126: Vsync And Field Configuration
ADV7850 sdp_hs_width[11:0], Addr 94 (sdp_IO), Address 0x96[3:0]; Address 0x97[7:0] The sdp_hs_width[11:0] bits allow the user to freely adjust the width of the HSync pulse within the video line. The values in the sdp_hs_width[11:0] bits are measured in pixel units from the falling edge of HSync. The position of this edge is controlled by placing an unsigned binary number into the sdp_hs_beg_adj[11:0] bits.
Page 127 ADV7850 FIELD/DE: • Polarity pin adjustments: sdp_vs_pol  sdp_fld_pol  • VSync timing adjustments relative to HSync: sdp_vsf_h_beg_adj[11:0]  sdp_vsf_h_mid_adj[11:0]  • VSync timing adjustments: sdp_vs_v_beg_o_adj[5:0]  sdp_vs_v_beg_e_adj[5:0]  sdp_vs_v_end_o_adj[5:0]  sdp_vs_v_end_e_adj[5:0]  sdp_vho_beg_inv  sdp_vho_end_inv  sdp_vhe_beg_inv  sdp_vhe_end_inv ...
Page 128 ADV7850 Function sdp_vsf_h_mid_adj[11: Description 0x000 << Default value sdp_vs_v_beg_o_adj[5:0], Addr 94 (sdp_IO), Address 0xA8[5:0] Adjust SDP VSync pin begin line relative to default, only +ve recommended, twos complement. Function sdp_vs_v_beg_o_adj[5: Description 000100 << Default value sdp_vs_v_beg_e_adj[5:0], Addr 94 (sdp_IO), Address 0xA9[5:0] Adjust SDP VSync pin begin line relative to default, only +ve recommended, 2s complement.
Page 129: De Configuration
ADV7850 Function sdp_fld_tog_e_adj[5:0] Description 000100 << Default value sdp_vho_beg_inv, Addr 94 (sdp_IO), Address 0xB0[0] A control to swap switch position of field and beginning of VSync on odd fields. Function sdp_vho_beg_inv Description 0 << Use default horizontal switch position for field and beginning of VSync on odd fields...
Page 130 ADV7850 sdp_de_h_end_adj[11:0]  sdp_de_pol, Addr 94 (sdp_IO), Address 0xB1[4] A control to change polarity of DE. Function sdp_de_pol Description Inverted DE polarity 1 << Default DE polarity sdp_de_v_beg_o_adj[5:0], Addr 94 (sdp_IO), Address 0xAC[5:0] Adjust SDP DE pin begin line relative to default, only +ve recommended, 2s complement.
Page 131: Csync Signal Configuration
ADV7850 sdp_de_h_end_adj[11:0] allows the user to adjust the horizontal DE trailing edge position relative to the HSync. The values are measured in pixel units from the falling edge of HSync. The position of the horizontal DE trailing edge is controlled by placing a twos complement number into the sdp_de_h_end_adj[11:0] bits.
Page 132: Manual Color Space Conversion Matrix
RGB, YUV, YcrCb, and many other color spaces. The CSC matrix in the ADV7850 is a 3 x 3 matrix with full programmability of all coefficients in the matrix in manual mode. Each coefficient is 12-bit wide to ensure signal integrity is maintained in the CSC section. The CSC contains three identical processing...
Page 133 ADV7850 Function sdp_csc_auto Description Use manual CSC coefficients 1 << Use automatic CSC coefficients sdp_csc_scale, Addr 94 (sdp_IO), Address 0xE0[7] This control is used to set the CSC gain. Function sdp_csc_scale Description 0 << CSC scaler set to 1 CSC scaler set to 2 This bit allows the control to accommodate coefficients that extend the supported range of the DPP.
Page 134 ADV7850 Function sdp_b1[12:0] Description 0x0000 << Default sdp_b2[12:0], Addr 94 (sdp_IO), Address 0xEA[4:0]; Address 0xEB[7:0] This control is used to set the CSC B2 coefficient for the SDP output color space converter. Function sdp_b2[12:0] Description 0x0926 << Default sdp_b3[12:0], Addr 94 (sdp_IO), Address 0xEC[4:0]; Address 0xED[7:0] This control is used to set the CSC B3 coefficient for the SDP output color space converter.
Page 135: Csc Manual Programming
ADV7850 Function sdp_c4[14:0] Description 0x0000 << Default 6.18.5.1 CSC Manual Programming This section outlines the settings for a conversion from NTSC YCrCb to RGB output. The CSC is only supported in these fixed settings: 94 97 00 HSync width Adjustment...
Page 136: Hdmi Receiver
7.1.1 In HDMI Mux mode the HDMI data is passed directly from the RX to the TX. In this mode the ADV7850 supports up to 3GHz inputs. All the InfoFrame data is automatically passed to the HDMI TX within the ADV7850 and output directly to the backend IC.
Page 137: Cable Detect
Cable detected on Port D (high level on rxd_5v) The ADV7850 provides a digital glitch filter on the +5 V power signals from the HDMI ports. The output of this filter is used to reset the HDMI block (refer to Section 7.42).
Page 138: Hot Plug Assert
7.3 HOT PLUG ASSERT The ADV7850 features hot plug assert (HPA) controls for its four HDMI ports. The purpose of these controls and their corresponding output pins is to communicate to an HDMI transmitter that the E-EDID connected to the DDC bus can be accessed.
Page 139 ADV7850 Function hpa_man_value_c Description 0  0 V applied to HPA_C pin High level applied to HPA_C pin hpa_man_value_d, IO, Address 0x20[4] This control is used to set the value of HPA on Port D. It is only valid if hpa_manual is set to 1.
Page 140 ADV7850 Function hpa_tristate_c Description 0  HPA_C pin active Tristate HPA_C pin hpa_tristate_d, IO, Address 0x20[0] This control is used to tristate the HPA output pin for Port D. Function hpa_tristate_d Description 0  HPA_D pin active Tristate HPA_D pin hpa_status_port_a, IO, Address 0x21[3] (Read Only) This readback displays the HPA status for Port A.
Page 141: E-Edid/Repeater Controller
Display Identification (E-EDID) to be functional and accessible through the DDC port even when the part is powered down. In the cable supply mode, all the power needed by the ADV7850 can be provided by one or more HDMI transmitters connected to the HDMI ports.
Page 142: E-Edid Data Configuration
7.5 E-EDID DATA CONFIGURATION The ADV7850 features an SRAM memory that can store an E-EDID. This internal E-EDID feature can be used for the four HDMI ports, A, B, C, and D. It is also possible to use an external device storage for the E-EDID data on each port, or a combination of internal E-EDID for some port(s) and external storage for the other port(s).
Page 143 When the internal E-EDID is enabled on any of the four ports (for example, Port A by setting man_edid_a_enable to 1), the ADV7850 must first calculate the E-EDID checksums for that port before the E-EDID is actually enabled. The following read only flags can be utilized to determine if the E-EDID is actually enabled on any of the four HDMI ports.
Page 144: E-Edid Support For Cable Supply Mode
E-EDID Support for Cable Supply Mode 7.5.1 The ADV7850 can support internal E-EDID access when no system power is present by using the +5 V supply available on the HDMI or VGA cable, if present. (Refer to Section for more details.) Using this feature, an application that integrates the ADV7850 can make its E-EDID available to an HDMI source.
Page 145: Spi Interface
Power switch takes the cable supply whenever it is available, otherwise the system supply 7.8 SPI INTERFACE The ADV7850 has a 4-pin SPI interface to load the E-EDID information from the SPI EEPROM into the internal E-EDID RAM: • EP_MOSI •...
Page 146: Spi Eeprom Data Structure
Write contents of internal E-EDID to SPI EEPROM The ADV7850 uses first 8 bits of EDID for its own purpose to load and store from the EEPROM. The register below lists the contents of the first 8 bits and their use. The customer should program to their system requirements...
Page 147: Structure Of Internal E-Edid For Porta
• After power up, the ADV7850 E-EDID/Repeater controller sets all bytes in the internal E-EDID RAM to 0. This operation takes less than 1 msec. It is recommended to wait for at least 1 ms before initializing the EDID Map with an E-EDID image.
Page 148: Figure 53: Port B E-Edid Structure And Mapping For Spa Located In E-Edid Block 1
• After power up, the ADV7850 E-EDID controller sets all bytes in the internal E-EDID RAM to 0. This operation takes less than 1 ms. It is recommended to wait for at least 1 ms before initializing the EDID Map with E-EDID.
Page 149 ADV7850 • spa_port_b[3:0] = D spa_port_b[15:0], Addr 64 (Repeater), Address 0x52[7:0]; Address 0x53[7:0] This control is used to define the source physical address for Port B. This is used for CEC and is located in the HDMI vendor specific data block in the E-EDID.
Page 150: Spa Configuration
The Equalizer provides two forms of signal correction. The first signal correct is to gain the full signal to the correct levels. In the ADV7850 this is called the GCTRL gain. After this stage, the signal is given a high frequency boost. In the ADV7850 this is called the ZCTRL gain.
Page 151: Port Selection
If an HDMI port is not selected by hdmi_port_select, this port is disabled by default. Asserting en_bg_port_x allows this unselected port to be enabled in background mode (where x is a, b, c or d). Once a port is in background mode, the ADV7850 establishes an HDCP link with its source even though it is not selected by hdmi_port_select.
Page 152 Disable port unless selected with hdmi_port_select Enable port in background mode The ADV7850 can also perform HDMI parameter measurements and packet detection on one background port. The following information can then be read from the background measurement parameter and background packet registers: •...
Page 153: Tmds Clock Activity Detection
7.16 TMDS CLOCK ACTIVITY DETECTION The ADV7850 provides circuitry to monitor TMDS clock activity on each of its four HDMI ports. The firmware can poll the appropriate registers for TMDS clock activity detection and configure the ADV7850 as desired.
Page 154: Clock And Data Termination Control
Clock and Data Termination Control 7.16.1 The ADV7850 provides controls for the TMDS clock and data termination on all HDMI ports. The ADV7850 also offers automatic or manual termination closure of the selected port, and individual manual control over the four ports.
Page 155: Tmds Measurement
Enable termination Port D 1  Disable termination Port D 7.17 TMDS MEASUREMENT The ADV7850 contains logic that measures the frequency of the TMDS clock transmitted on the TMDS clock channel. The TMDS frequency can be read back via the tmdsfreq[8:0] tmdsfreq_frac[6:0] registers.
Page 156 TMDS frequency on the selected HDMI port changes by a programmable threshold • The ADV7850 can be configured to trigger an interrupt when new_tmds_frq_raw changes from 0 to 1. tmdsfreq[8:0], Addr 68 (HDMI), Address 0x51[7:0]; Address 0x52[7] (Read Only) This readback provides a full precision integer TMDS frequency measurement.
Page 157 ADV7850 Function tmds_pll_locked Description 0  TMDS PLL not locked TMDS PLL locked to TMDS clock input of selected HDMI port tmdspll_lck_a_raw, IO, Address 0x6A[7] (Read Only) This readback indicates the raw status of the Port A TMDS PLL lock signal.
Page 158: Deep Color Mode Support
7.18 DEEP COLOR MODE SUPPORT The ADV7850 supports HDMI streams with 24 bits per sample and deep color modes of 30 or 36 bits per sample. The addition of a video FIFO (refer to Section 7.19) allows for the robust support of these modes.
Page 159 • The ADV7850 can be configured to trigger an interrupt when deep_color_chng_raw changes from 0 to 1. In that configuration, the interrupt status deep_color_chng_st indicates that deep_color_chng_raw has changed from 0 to 1. Refer to Section additional information on the configuration of interrupts.
Page 160: Video Fifo
12-bit color per channel 16-bit color per channel 7.19 VIDEO FIFO The ADV7850 contains a FIFO located between the incoming TMDS data and the CP core (refer to Figure 55). Data arriving over the HDMI link will be at 1X for non deep color mode (24 bits), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively).
Page 161: Pixel Repetition
In HDMI mode, video formats with TMDS rates below 25 Mpixels/s require pixel repetition in order to be transmitted over the TMDS link. When the ADV7850 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the AVI InfoFrame.
Page 162 ADV7850 When hdmi_pixel_repetition is non zero, video pixel data is discarded and the pixel clock frequency is divided by (hdmi_pixel_repetition) + 1. hdmi_pixel_repetition[3:0], Addr 68 (HDMI), Address 0x05[3:0] (Read Only) This readback provides the current HDMI pixel repetition value decoded from the AVI InfoFrame received. The HDMI receiver automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value.
Page 163: Arc Support
1010 - 1111 Reserved 7.21 ARC SUPPORT The ADV7850 supports four single mode ARC channels. The input for the ARC transmitters is supplied by the SPDIF_IN pin. The ARC transmitters can be powered down using the following controls. arc_pwrdn_a[1], IO, Address 0xAC[0] This control is used to power down the ARC transmitter.
Page 164 ADV7850 transmitter using the following controls. zero_spdif_in_a, IO, Address 0xAD[0] This control is used to zero the SPDIF input to the ARC transmitter. Function zero_spdif_in_a Description Zero SPDIF input to ARC Tx channel A zero_spdif_in_b, IO, Address 0xAD[1] This control is used to zero the SPDIF input to the ARC transmitter.
Page 165: Video Support
 The ADV7850 receiver can support all mandatory HDMI 1.4a 3D formats, and many more. The 3D video format is indicated using the Video Identification Code (VIC) in the AVI InfoFrame (indicating the video format of one of the 2D pictures, as defined in CEA-861-D) in conjunction with the 3D_Structure field in the HDMI Vendor Specific InfoFrame (indicating the 3D structure).
Page 166 The ADV7850 supports the 1.1_features, fast_reauthentication, and fast_i2c speed HDCP features. The bcaps register must be initialized appropriately if these features are to be supported by the application integrating the ADV7850. For example, bcaps[0] is set to 1 to support fast_reauthentication.
Page 167: Internal Hdcp Key Otp Rom
After a power up, the ADV7850 reads the KSV from the internal HDCP ROM (refer to Figure • After a KSV update from an HDCP transmitter, the ADV7850 reads the KSV and all keys in order to carry out the link verification response (refer to Figure The host processor can read the hdcp_keys_read and hdcp_key_error flags to check that the ADV7850 successfully accessed the HDCP ROM.
Page 168: Figure 56: Hdcp Rom Access After Power Up
ADV7850 START (After power up) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 Read KSV and checksum CS1 from HDCP OTP ROM Derive checksum CS1' from CS1 = CS1' HDCP_KEY_ERROR = 1 Set BksV (HDCP register Address 0x00) Bksv = KSV HDCP_KEY_READ = 1...
Page 169: Hdmi Synchronization Parameters
ADV7850 while it reads the HDCP keys and/or the KSV from the internal HDCP ROM. • A hardware reset (that is, reset via the RESET pin) does not lead the ADV7850 to read the KSV or the keys from the HDCP ROM.
Page 170 ADV7850 de_regen_filter_locked, Addr 68 (HDMI), Address 0x07[5] (Read Only) This readback displays the DE regeneration filter lock status. It indicates if the DE regeneration section has locked to the received DE and if the horizontal synchronization parameter measurements are valid for readback.
Page 171: Background Port Horizontal Filter Measurements
ADV7850 Function hsync_pulse_width[12: Description xxxxxxxxxxx Total number of pixels in HSync pulse hsync_back_porch[12:0], Addr 68 (HDMI), Address 0x24[4:0]; Address 0x25[7:0] (Read Only) This readback displays the total number of pixels in the back porch. The HSync back porch width is a horizontal synchronization measurement.
Page 172: Horizontal Filter Locking Mechanism
Vertical Filters and Measurements 7.24.5 The ADV7850 integrates an HDMI vertical filter which performs measurements on the VSync of the HDMI stream on the selected port. The ADV7850 also performs vertical measurements on the background port as selected by bg_meas_port_sel[2:0].These measurements are available in the HDMI Map and can be used to determine the resolution of the incoming video data streams.
Page 173 ADV7850 vert_filter_locked, Addr 68 (HDMI), Address 0x07[7] (Read Only) This readback indicates whether or not the vertical filter is locked and the vertical synchronization parameter measurements are valid for readback. Function vert_filter_locked Description 0  Vertical filter not locked Vertical filter locked v_locked_raw, IO, Address 0x74[1] (Read Only) This readback indicates the raw status of the vertical sync filter locked signal.
Page 174: Figure 59: Vertical Parameters For Field 0
ADV7850 field0_vs_back_porch[13:0], Addr 68 (HDMI), Address 0x32[5:0]; Address 0x33[7:0] (Read Only) This readback displays the total number of half lines in the VSync back porch of Field 0. The Field 0 VSync back porch width is a vertical synchronization measurement. The unit for this measurement is half lines.
Page 175 ADV7850 Function field1_total_height[13: Description 00000000000000  Total number of half lines in Field 1 (divide readback by 2 to get number of lines) xxxxxxxxxxxxxx Total number of half lines in Field 1 (divide readback by 2 to get number of lines) field1_height[12:0], Addr 68 (HDMI), Address 0x0B[4:0];...
Page 176: Background Port Vertical Filter Measurements
ADV7850 Function field1_vs_back_porch[1 Description 3:0] 00000000000000  Number of half lines in VSync back porch of Field 1 (divide readback by 2 to get number of lines) xxxxxxxxxxxxxx Number of half lines in VSync back porch of Field 1 (divide readback by 2 to get number of...
Page 177: Vertical Filter Locking Mechanism
(that is, audio sample, DSD, DST or HBR packets) encapsulated inside the HDMI data stream. The ADV7850 also regenerates an audio master clock along with the extraction of the audio data. The clock regeneration is performed by an integrated DPLL. The regenerated clock is used to output audio data from the 127 stereo sample depth FIFO to the audio interface configuration pins.
Page 178: Audio Dpll
TMDS PLL is locked (refer to tmds_pll_locked) • ADV7850 has received an ACR packet with the N and CTS parameters within a valid range The audio DPLL lock status can be monitored via audio_pll_locked. audio_pll_locked, Addr 5C (audio_codec), Address 0x0D[0] (Read Only) This readback indicates the audio PLL locking status.
Page 179: Audio Dpll Coast Feature
ADV7850 Audio DPLL Coast Feature 7.25.4 The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio master clock when selectable events occur. The coast feature allows the audio DPLL to provide an audio master clock when the audio processor mutes the audio following a mute condition (refer to Section 7.31).
Page 180 ADV7850 fifo_underflo_raw, IO, Address 0x7E[6] (Read Only) This readback indicates the status of audio FIFO underflow interrupt signal. When set to 1, it indicates the Audio FIFO read pointer has reached the write pointer causing the audio FIFO to underflow. Once set, this bit remains high until it is cleared.
Page 181: Audio Packet Type Flags
DST packets • HBR packets The following flags are provided to monitor the type of audio packets received by the ADV7850. Figure 63 shows the algorithm that can be implemented to monitor the type of audio packet processed by the ADV7850.
Page 182 DST sample rate equals transfer rate DST sample rate doubles transfer rate Notes: • The ADV7850 processes only one type of audio packet at a time. • The ADV7850 processes the latest type of audio packet that it received. •...
Page 183: Audio Output Interface
H B R pa cke ts ar e be ing r e ce ive d Figure 63: Monitoring Audio Packet Type Processed by ADV7850 7.28 AUDIO OUTPUT INTERFACE The ADV7850 has a dedicated eight pin audio output interface. The output pin names and descriptions are shown in Table Table 14: Audio Outputs and Clocks...
Page 184: I2S/Spdif Audio Interface And Output Controls
ADV7850 The audio output interface can be adjusted into numerous configurations for the different audio formats. This flexibility helps to increase interconnectivity with downstream audio devices and HDMI transmitters. Table 15 shows the default configurations for the various possible output interfaces.
Page 185 Right justified Left justified Raw SPDIF (IEC60958) Mode Notes: i2soutmode is effective when the ADV7850 is configured to output I2S streams or AES3 streams. This is the case in the following situations: • The ADV7850 receives audio sample packets. •...
Page 186: Figure 64: Timing Audio Data Output In I
ADV7850 Table 18: I S/SPDIF Interface Description S/SPDIF Interface IO Function SPDIF0 SPDIF audio output I2S0/SDPIF0 S audio (channel 1, 2) / SPDIF0 I2S1/SDPIF1 S audio (channel 3, 4) / SPDIF1 I2S2/SDPIF2 S audio (channel 5, 6) / SPDIF2 I2S3/SDPIF3...
Page 187: Dsd Audio Interface And Output Controls
DSD Audio Interface and Output Controls 7.28.2 The ADV7850 incorporates a 6-DSD channel interface used to output the audio stream extracted from DSD packets. Each of the DSD channels carries an over-sampled 1-bit representation of the audio signal as delivered on Super Audio CDs (SACDs).
Page 188: Figure 70: Dsd Timing Diagram
Where xx is the channel, for example, 0A, 0B By default, the ADV7850 automatically enables the DSD interface if it receives DSD packets. The ADV7850 also automatically enables the I2S interface if it receives audio sample packets or if it does not receive any audio packets. However, it is possible to override the audio...
Page 189: Dst Audio Interface And Output Controls
DST Audio Interface and Output Controls 7.28.3 The ADV7850 incorporates a DST interface that outputs audio data extracted from DST packets. The transfer rate of the DST packets is indicated via dst_double. dst_double, Addr 68 (HDMI), Address 0x19[2] (Read Only) This readback indicates when the DST audio is double data rate.
Page 190: Hbr Interface And Output Controls
Figure 72: DST Timing Diagram for DST_DOUBLE = 1 HBR Interface and Output Controls 7.28.4 The ADV7850 can receive HBR audio stream packets. The ADV7850 outputs HBR data over five of the audio output pins in any of the following formats: •...
Page 191: Mclkout Setting
ADV7850 Function ovr_mux_hbr Description 0  Automatic HBR output control Manual HBR output control mux_hbr_out, Addr 68 (HDMI), Address 0x01[1] This control is used to manually select the audio output interface for HBR data. It is valid when ovr_mux_hbr is set to 1.
Page 192: Audio Muting
7.31 AUDIO MUTING The ADV7850 integrates an advanced audio mute function that is designed to remove all extraneous noise and pops from a 2-channel L- PCM audio stream at sample frequencies up to 192 kHz. The audio mute controller takes in event detection signals that can be used to determine when an audio mute is needed.
Page 193: Table 24: Selectable Mute Conditions
ADV7850 audio_mute_speed[4:0], Addr 68 (HDMI), Address 0x0F[4:0] This control is used to define the number of samples between each volume change of 1.5 dB when muting and unmuting. Function audio_mute_speed[4:0] Description xxxxx Number of samples between each volume change of 1.5 dB not_auto_unmute, Addr 68 (HDMI), Address 0x1A[0] This control is used to disable the auto unmute feature.
Page 194: Internal Mute Status
The ADV7850 discards audio sample packets that have an incorrect parity bit. When these samples are received, the ADV7850 repeats the previous audio sample with a valid parity bit. The audio stream out of the ADV7850 can be muted in this situation if the audio mute mask mt_msk_parity_err is set.
Page 195: Audio Clock Regeneration Parameters
Audio mute occurs if audio sample packet is received with incorrect parity bit. 7.32 AUDIO CLOCK REGENERATION PARAMETERS The ADV7850 recreates an internal audio master clock using Audio Clock Regeneration (ACR) values transmitted by the HDMI source. ACR Parameters Readbacks 7.32.1...
Page 196: Channel Status
ADV7850 Function change_n_raw Description 0  Audio clock regeneration N value not changed Audio clock regeneration N value changed cts_pass_thrsh_raw, IO, Address 0x7E[4] (Read Only) This readback indicates the status of the ACR CTS value exceed threshold interrupt signal. When set to 1, it indicates the CTS value of the ACR packets has exceeded the threshold set by cts_change_threshold.
Page 197: General Control And Mode Information
ADV7850 Start Enable the CS_DATA_VALID_ST Initialization interrupt CS_DATA_VALID_S T set to 1 ? Check if the CS_DATA_VALID Set CS_DATA_VALID_CLR to 1 interrupt has triggered CS_DATA_VALID_R AW set to 1 Read the channel status bits in HDMI The channel status bits previously...
Page 198: Category Code
ADV7850 cs_data[2], Copyright, HDMI Map, Address 0x36, [2] Function cs_data[2] Description 0 << Software for which copyright is asserted Software for which no copyright is asserted cs_data[5:3], Emphasis, HDMI Map, Address 0x36, [5:3] Function cs_data[5:3] Description 000 << Two audio channels without pre-emphasis...
Page 199: Word Length
ADV7850 cs_data[27:24], Sampling Frequency, HDMI Map, Address 0x39, [3:0] Function cs_data[27:24] Description 0000 << 44.1 kHz 0010 48 kHz 0011 32 kHz 1000 88.2 kHz 1010 96 kHz 1100 176 kHz 1110 192 kHz Unspecified values are reserved cs_data[29:28], Clock Accuracy, HDMI Map, Address 0x39, [5:4]...
Page 200: Monitoring Change Of Audio Sampling Frequency
7.34 PACKETS AND INFOFRAMES REGISTERS In HDMI, auxiliary data is carried across the digital link using a series of packets. The ADV7850 automatically detects and stores the following HDMI packets: •...
Page 201: Infoframes Registers
InfoFrame Collection Mode 7.34.2 The ADV7850 has two modes for storing the InfoFrame packet sent from the source into the internal memory. By default, the ADV7850 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame.
Page 202: Avi Infoframe Registers
ADV7850 Function spd_inf_cks_err_raw Description 0  No SPD InfoFrame checksum error occurred SPD InfoFrame checksum error occurred ms_inf_cks_err_raw, IO, Address 0x88[7] (Read Only) This readback indicates the status of the MPEG source InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error was detected for an MPEG source InfoFrame.
Page 203: Audio Infoframe Registers
ADV7850 InfoFrame Access Type Register Name Byte Name Map Address 0x13 avi_inf_pb_0_20 Data Byte 19 0x14 avi_inf_pb_0_21 Data Byte 20 0x15 avi_inf_pb_0_22 Data Byte 21 0x16 avi_inf_pb_0_23 Data Byte 22 0x17 avi_inf_pb_0_24 Data Byte 23 0x18 avi_inf_pb_0_25 Data Byte 24...
Page 204: Spd Infoframe Registers
ADV7850 SPD InfoFrame Registers 7.34.6 Table 27 provides a list of readback registers available for the Source Product Descriptor (SPD) InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 27: SPD InfoFrame Registers...
Page 205: Vendor Specific Infoframe Registers
ADV7850 Table 28: MPEG InfoFrame Registers InfoFrame Access Register Name Byte Name Map Address Type 0xE9 ms_packet_id[7:0] Packet Type Value 0xEA ms_inf_vers InfoFrame version number 0xEB ms_inf_len InfoFrame length 0x46 ms_inf_pb_0_1 Checksum 0x47 ms_inf_pb_0_2 Data Byte 1 0x48 ms_inf_pb_0_3 Data Byte 2...
Page 206: Multiple Infoframes Support ( Thx Media Director™)
HDMI specification defines only one Vendor Specific InfoFrame (VSI) per frame. For support of some inputs which use THX Media Director, it is required to be able to receive three VSIs at the same time. The ADV7850 can detect the number of incoming VSIs and select which VSI to decode, load it into the buffer, read it in the system, and then select another VSI to be decoded and loaded into the buffer.
Page 207: Packet Registers
ADV7850 Function en_pkt_cnt_sel Description 0  Disabled, collect every packet as it is received Enable selectively collecting one of multiple packets per frame of the same type pkt_cnt_sel[3:0], Addr 7C (InfoFrame), Address 0xFE[3:0] This control selects which one of the multiple received packets per frame of type pkt_cnt_id is to be collected. It must be enabled with en_pkt_cnt_sel.
Page 208: Isrc Packet Registers
ADV7850 InfoFrame Register Name Packet Byte No. Map Address 0x7D acp_pb_0_14 PB13 0x7E acp_pb_0_15 PB14 0x7F acp_pb_0_16 PB15 0x80 acp_pb_0_17 PB16 0x81 acp_pb_0_18 PB17 0x82 acp_pb_0_19 PB18 0x83 acp_pb_0_20 PB19 0x84 acp_pb_0_21 PB20 0x85 acp_pb_0_22 PB21 0x86 acp_pb_0_23 PB22 0x87...
Page 209: Table 32: Isrc2 Packet Registers
ADV7850 InfoFrame Register Name Packet Byte No. Map Address 0x9F isrc1_pb_0_20 PB19 0xA0 isrc1_pb_0_21 PB20 0xA1 isrc1_pb_0_22 PB21 0xA2 isrc1_pb_0_23 PB22 0xA3 isrc1_pb_0_24 PB23 0xA4 isrc1_pb_0_25 PB24 0xA5 isrc1_pb_0_26 PB25 0xA6 isrc1_pb_0_27 PB26 0xA7 isrc1_pb_0_28 PB27 As defined by the HDMI 1.4 specifications...
Page 210: Gamut Metadata Packets
ADV7850 The ISRC2 packet registers are considered valid if, and only if, isrc2_pckt_raw is set to 1. isrc2_pckt_raw, IO, Address 0x60[7] (Read Only) This readback indicates the raw status signal of the International Standard Recording Code 2 (ISRC2) Packet detection signal. This bit resets to 0 after an HDMI packet detection reset or upon writing to isrc2_packet_id.
Page 211: Customizing Packet/Infoframe Storage Registers
The packet type value of each set of packet and InfoFrame registers in the InfoFrame Map is programmable. This allows the user to configure the ADV7850 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port.
Page 212 ADV7850 ms_packet_id[7:0], Addr 7C (InfoFrame), Address 0xE9[7:0] This control is used to set the MPEG source InfoFrame ID. Function ms_packet_id[7:0] Description 0xxxxxxx Packet type value of packet stored in InfoFrame Map, Address 0x46 to 0x53 1xxxxxxx Packet type value of InfoFrame stored in InfoFrame Map, Address 0x46 to 0x53 vs_packet_id[7:0], Addr 7C (InfoFrame), Address 0xEC[7:0] This control is used to set the Vendor Specific InfoFrame ID.
Page 213: Background Port Infoframe And Packet Support
• 0x09: HBR Audio Stream Packet 7.37 BACKGROUND PORT INFOFRAME AND PACKET SUPPORT The ADV7850 can provide limited information on the packets received on the background port via the following controls and readback registers. bg_header_requested[7:0], Addr 68 (HDMI), Address 0xEF[7:0] This control is used to select the type of InfoFrame/packet to be provided for readback in the background port header and packet registers (0xF0 to 0xF5).
Page 214: Repeater Support
The ADV7850 incorporates an E-EDID/Repeater controller that provides all the features required for a receiver front end of a fully HDCP 1.3 compliant repeater system. The ADV7850 has a RAM that can store up to 128 KSVs, which allows it to handle up to 128 downstream devices in repeater mode.
Page 215: Repeater Actions Required By External Controller
Repeater Actions Required by External Controller 7.38.2 The external controller must set the bcaps register and notify the ADV7850 when the KSV list is updated, as described in the following actions Note that many more routines must be implemented into the external controller driving the ADV7850 to implement a full repeater. Such...
Page 216: Hdcp Registers Available In Repeater Map
Detected write access to AKSV register on Port D Second and Subsequent AKSV Updates When the upstream transmitter writes its AKSV for the second time or more into the ADV7850 HDCP registers, the external controller driving the ADV7850 should set ksv_list_ready to 1.
Page 217 ADV7850 auto_hdcp_map_enable, Addr 64 (Repeater), Address 0x79[3] This control is used to select the port to be accessed for HDCP addresses, i.e. the HDMI active port (selected by hdcp_port_select in the HDMI Map), or the port selected in hdcp_map_select. Function...
Page 218: Table 34: Register Location For Sha_1 Hash Value
All registers specified in table are located in the Repeater Map Refer to HDCP Protection System Standards The ADV7850 supports up to 25 KSVs (0 through to 24). The complete set of bytes is listed below. Each KSV is 40bits long and the first KSV starts at address 0x80.
Page 219 ADV7850 KSV Byte Register Name Address ksv_byte18 ksv_byte19 ksv_byte20 ksv_byte21 ksv_byte22 ksv_byte23 ksv_byte24 ksv_byte25 ksv_byte26 ksv_byte27 ksv_byte28 ksv_byte29 ksv_byte30 ksv_byte31 ksv_byte32 ksv_byte33 ksv_byte34 ksv_byte35 ksv_byte36 ksv_byte37 ksv_byte38 ksv_byte39 ksv_byte40 ksv_byte41 ksv_byte42 ksv_byte43 ksv_byte44 ksv_byte45 ksv_byte46 ksv_byte47 ksv_byte48 ksv_byte49 ksv_byte50 ksv_byte51...
Page 220 ADV7850 KSV Byte Register Name Address ksv_byte62 ksv_byte63 ksv_byte64 ksv_byte65 ksv_byte66 ksv_byte67 ksv_byte68 ksv_byte69 ksv_byte70 ksv_byte71 ksv_byte72 ksv_byte73 ksv_byte74 ksv_byte75 ksv_byte76 ksv_byte77 ksv_byte78 ksv_byte79 ksv_byte80 ksv_byte81 ksv_byte82 ksv_byte83 ksv_byte84 ksv_byte85 ksv_byte86 ksv_byte87 ksv_byte88 ksv_byte89 ksv_byte90 ksv_byte91 ksv_byte92 ksv_byte93 ksv_byte94 ksv_byte95...
Page 221: Interface To Dcm Section
ADV7850 KSV Byte Register Name Address ksv_byte106 ksv_byte107 ksv_byte108 ksv_byte109 ksv_byte110 ksv_byte111 ksv_byte112 ksv_byte113 ksv_byte114 ksv_byte115 ksv_byte116 ksv_byte117 ksv_byte118 ksv_byte119 ksv_byte120 ksv_byte121 ksv_byte122 ksv_byte123 ksv_byte124 ksv_byte125 ksv_byte126 ksv_byte127 All registers specified in table are located in the Repeater Map. 7.39 INTERFACE TO DCM SECTION The video data from the HDMI section is sent to the CP section via the DCM block.
Page 222: Color Space Information Sent To The Cp Section
ADV7850 / Cb / Cr / Cb / Cr / Cb / Cr / Cb / Cr / Cb / Cr Component Channel Bit 12-0 Bit 12-0 Bit 12-0 Figure 75: Video Stream Output by HDMI Core for YC 4:2:2 Input and UP_CONVERSION = 0 up_conversion_mode, Addr 68 (HDMI), Address 0x1D[5] This control is used to select linear or interpolated 4:2:2 to 4:4:4 conversion.
Page 223: Table 36: Hdmi Flags In Io Map Register 0X60
Returns 1 if latest general control packet received has av_mute asserted. Reset to 0 following a packet detection flag reset condition. (Refer to Section 7.43.) internal_mute_raw Returns 1 if ADV7850 has internally muted the audio data. Additional information available on page 194. cs_data_valid_raw 7 (MSB) Returns 1 if channel status bit readback registers in HDMI Map, Address 0x36 to 0x3A are valid.
Page 224: Table 41: Hdmi Flags In Io Map Register 0X79
ADV7850 Table 41: HDMI Flags in IO Map Register 0x79 Bit Name Bit Position new_avi_info_raw 0 (LSB) new_audio_info_raw new_spd_info_raw new_ms_info_raw new_vs_info_raw new_acp_pckt_raw new_isrc1_pckt_raw new_isrc2_pckt_raw 7 (MSB) Table 42: HDMI Flags in IO Map Register 0x7E Bit Name Description Position new_gamut_mdata_raw 0 (LSB) When set to 1, indicates that Gamut Metadata packet with new content received.
Page 225: Hdmi Receiver Section Reset Strategy
1. 7.43 HDMI PACKET DETECTION FLAG RESET A packet detection flag reset is triggered when any of the following events occur: • The ADV7850 is powered up. • The ADV7850 is reset. • A TMDS clock is detected after a period of no clock activity on the selected HDMI port.
Page 226: Decimation Controls, Color Space Conversion, And Color Controls
ADV7850 8 DECIMATION CONTROLS, COLOR SPACE CONVERSION, AND COLOR CONTROLS 8.1 DCM CONFIGURATION The DCM is a fully automated block which can fully configure its inputs based on the primary mode and video standard settings. The configuration of the primary mode and video standard are described in Section 4.
Page 227: Manual Filter Coefficient Programming
CVBS 8.2 MANUAL FILTER COEFFICIENT PROGRAMMING The ADV7850 allows the user to fully program the DCM filters on each of the channels. The user can select between a 19/20 tap or 39/40 tap filter. Follow these steps to manually program a channel. (In this example, Channel 2 is programmed with a 39 tap filter.) Enable the selection of a manual filter by setting dcm_filt_en.
Page 228 ADV7850 dcm_filt_sel[2:0], Addr A0 (VFE), Address 0x21[2:0] This control is used to manually select a filter for the DCM filter block. The particular channel should be selected by filt_sel before this control is set. Function dcm_filt_sel[2:0] Description 000  Reserved...
Page 229: Dcm Channel Power Down Control
DCM Channel Power Down Control 8.2.1 The ADV7850 allows for individual control of the DCM channels. The power-down controls are enabled by dcm_ch_en. dcm_ch_enable, Addr A0 (VFE), Address 0x23[7] This control is used to provide manual control of the DCM channels.
Page 230: Color Space Conversion Matrix
The CP also provides color controls for brightness, contrast, saturation and hue adjustments. The CP CSC is the main color space converter. The CPP block also has an automatic non programmable CSC. The ADV7850 will automatically configure the fixed CSC for certain modes, depending on the input and output formats and the use of the color control feature.
Page 231: Selecting Automatic Or Manual Cp Csc Conversion Mode
Reserved The CSC configuration mode is automated in the ADV7850. Automatic or manual CSC mode can be selected by setting the csc_coeff_sel[3:0] bits. When csc_coeff_sel[3:0] is set to 0b1111, the CSC mode is automatically selected, based on the input color space and output color space required and set through the following registers: •...
Page 232: Table 47: Automatic Input Color Space Selection
ADV7850 Table 47: Automatic Input Color Space Selection prim_mode[3:0] vid_std[5:0] Input Color Space Input Range Comments 0001 ≤ 1001 YcrCb601 0:255 Analog SD/ED modes 0001 > 1001 YcrCb709 0:255 Analog HD modes 0010 xxxx 0:255 Analog GR modes 0101 xxxx...
Page 233: Manual Color Space Conversion Matrix
8.3.4 The CP CSC matrix in the ADV7850 is a 3 x 3 matrix with full programmability of all coefficients in the matrix in manual mode. Each coefficient is 12-bits wide to ensure signal integrity is maintained in the CP CSC section. The CP CSC contains three identical processing channels, one of which is shown in Figure 77.
Page 234: Table 50: Csc Coefficients
ADV7850 Table 50: CSC Coefficients Control CP Map Address Reset Value (Hex) Description A1[12:0] 0x57 [4:0], 0x58 [7:0] 0x800 Coefficient for channel A A2[12:0] 0x55 [1:0], 0x56 [7:0] 0x57 [7:5] 0x000 Coefficient for channel A A3[12:0] 0x54 [6:0], 0x55 [7:2]...
Page 235 ADV7850 Function rb_a3[12:0] Description xxxxxxxxxxxxx Readback value rb_a4[12:0], Addr 44 (CP), Address 0x0B[4:0]; Address 0x0C[7:0] (Read Only) This readback displays the CSC coefficient A4 modified by the video adjustment block. Function rb_a4[12:0] Description xxxxxxxxxxxxx Readback value rb_b1[12:0], Addr 44 (CP), Address 0x17[4:0]; Address 0x18[7:0] (Read Only) This readback displays the CSC coefficient B1 modified by the video adjustment block.
Page 236: Csc Manual Programming
ADV7850 Function rb_c2[12:0] Description xxxxxxxxxxxxx Readback value rb_c3[12:0], Addr 44 (CP), Address 0x1B[6:0]; Address 0x1C[7:2] (Read Only) This readback displays the CSC coefficient C3 modified by the video adjustment block. Function rb_c3[12:0] Description xxxxxxxxxxxxx Readback value rb_c4[12:0], Addr 44 (CP), Address 0x19[4:0]; Address 0x1A[7:0] (Read Only) This readback displays the CSC coefficient C4 modified by the video adjustment block.
Page 237: Csc Example
ADV7850 To support larger coefficients, the csc_scale[1:0] function should be used. Determine the setting for csc_scale[1:0] and adjust coefficients, if necessary. Program the coefficient values. Convert the float point coefficients into 12-bit fixed decimal format. Convert into binary format, using twos complement for negative values.
Page 238: Csc In Pass-Through Mode
 A1 = B2 = C3 = 0x800 (default value)  Note: The DPP CSC is always in pass-through mode unless the ADV7850 is processing an RGB input, outputting this input in the RGB color space and vid_adj_en is enabled.
Page 239 ADV7850 Function vid_adj_en Description 0  Disable color controls Enable color controls cp_contrast[7:0], Addr 44 (CP), Address 0x3A[7:0] This control is used to set the contrast. It is an unsigned value represented in a 1.7 binary format. The MSB represents the integer part of the contrast value, which is either 0 or 1.
Page 240 ADV7850 ⋅ − Equation 9: Hue in Degree Unit Applied to Chroma via cp_hue[7:0] Control Rev. A May 2012...
Page 241: Component Processor
H S y n c De p th Figure 78: Component Processor Block Diagram 9.1 INTRODUCTION TO COMPONENT PROCESSOR A simplified block diagram of the CP on the ADV7850 is shown in Figure 78. Data is supplied to the CP from the Data Preprocessor (DPP).
Page 242: Clamp Operation
ADV7850 9.2 CLAMP OPERATION For analog signals that enter the CP block, there are two clamp methods applied to the video signal: • An analog voltage clamp block prior to the ADCs • A digital fine clamp that operates after the DPP block The analog voltage clamp signal operates on the input video prior to digitization.
Page 243 ADV7850 clmp_a_man, Addr 44 (CP), Address 0x6C[7] This control is used to enable manual clamping for channel A. Function clmp_a_man Description 0  Use digital fine clamp value determined by on-chip clamp loop Ignore internal digital fine clamp loop result, use clmp_a[11:0] clmp_a[11:0], Addr 44 (CP), Address 0x6C[3:0];...
Page 244: Cp Gain Operation
The ADV7850 provides a special filter option for the auto clamp mode. The purpose of this filter is to provide a smoothening mechanism when the clamping value for each channel is being changed continuously in significant amounts by the autoclamping mechanism.
Page 245: Manual Gain Control
ADV7850 • Manual Gain Configuration This configuration is enabled by setting agc_mode_man to 1 and gain_man to 1. In this case the gain applied to the video data processed by the CP core is configured via the control registers a_gain[9:0], b_gain[9:0] and c_gain[9:0].
Page 246 ADV7850 is the floor function that returns the largest integer not greater than its input parameter floor X refers to A, B, and C Equation 10: CP Manual Gain Example: Example Gain a_gain[9:0] 0x80 0.98887 0xFD 0x280 gain_man, Addr 44 (CP), Address 0x73[7] This control is used to enable the gain factor to be set by the AGC or manually.
Page 247: Manual Gain Filter Mode
9.3.5 The ADV7850 provides a special filter option for the manual gain mode. This is functional only when manual gain is enabled. The purpose of this filter is to be a smoothing mechanism when the manual gain value is updated continuously by an external system based on either external or readback conditions in the ADV7850.
Page 248 ADV7850 An error signal is derived from the comparison of the measured synchronization depth and the target value. The error signal is weighted by a factor that allows different response times to be selected (agc_tim[2:0] is used to select different time constants). The resulting gain value is applied to all three channels A, B, and C.
Page 249: Readback Signals From Agc Block
ADV7850 Function agc_tim[2:0] Description 000  100 lines 1 frame 0.5 sec 1 sec 2 sec 3 sec 5 sec 7 sec 9.3.6.1 Readback Signals from AGC Block The following readback signals are provided: • Presently used gain value can be read back through cp_agc_gain[9:0] •...
Page 250: Table 51: Op_656_Range Description For Analog Front End Input Mode
ADV7850 Function hsd_chb[9:0] Description xxxxxxxxxx Readback for measured value of HSync depth on channel B hsd_chc[9:0], Addr 44 (CP), Address 0xE7[5:4]; Address 0xEA[7:0] (Read Only) This readback displays the measured value of the HSync depth on channel C before the gain multiplier. The value is presented in 1.9 binary format.
Page 251 CP Peak Active Video Readback The ADV7850 provides circuitry that monitors the active CP video on a field basis and records the largest value encountered during this time. It is intended to be used in a peak-white type AGC for signals that do not have an embedded horizontal synchronization pulse, and to provide feedback on the accurate function of the built-in AGC loop.
Page 252: Cp Offset Block
The actual offset used can come from two different sources: The ADV7850 includes an automatic selection of the offset value, dependent on the CSC mode that is programmed by the user. agc_tar_man op_656_range are used to derive offset values.
Page 253: Cp Data Path For Analog Mode
9.5.1 To compensate for signal attenuation in the analog front end of the ADV7850 and input buffer gain, a pregain block is provided in the CP path. The pregain block is controlled by cp_mode_gain_adj[7:0], which represents an unsigned value in a 1.7 binary format. The range of cp_mode_gain_adj[7:0] is 0 to 1.99.
Page 254 ADV7850 cp_mode_gain_adj[7:0], Addr 44 (CP), Address 0x40[7:0] This control is used for pregain adjustment to compensate for the gain of the Analog Front End. It stores a value in a 1.7 binary format. Function cp_mode_gain_adj[7:0] Description 0xxxxxxx Gain of (0 + (xxxxxxx / 128)) 10000000 Default pregain (pregain of 1.0)
Page 255: Figure 82: Cp Data Path Channel A (Y) For Analog Mode
ADV7850 Analog Input measured-value CLAMP MEASUREMENT 12-bit unsigned 12-bit unsigned 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit RGB_OUT CLAMP CLMP_A[11:0] CLMP_A_MAN 12’d0 auto-value 10’d2048 (16@8bit) CP_CLMP_EN AGC_MODE_MAN CP_MODE_GAIN_ADJ[7:0] 13-bit signed 13-bit signed GAIN_MAN 8-bit A_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit...
Page 256: Figure 83: Cp Data Path Channel B/C (Uv) For Analog Mode
ADV7850 Analog Input measured-value CLAMP MEASUREMENT 12-bit unsigned 12-bit unsigned 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit RGB_OUT CLAMP CLMP_B[11:0]/CLMP_C[11:0] CLMP_BC_MAN 12’d0 auto-value 10’d2048 (16@8bit) CP_CLMP_EN AGC_MODE_MAN CP_MODE_GAIN_ADJ[7:0] 13-bit signed 13-bit signed GAIN_MAN 8-bit B_GAIN[9:0]/C_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit...
Page 257: Figure 84: Cp Data Path Channel A/B/C (Rgb) For Analog Mode
ADV7850 Analog Input measured-value CLAMP MEASUREMENT 12-bit unsigned 12-bit unsigned 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit RGB_OUT CLMP_A[11:0]/CLMP_B[11:0]/CLMP_C[11:0] CLAMP CLMP_A_MAN/CLMP_BC_MAN 12’d0 auto-value 10’d2048 (16@8bit) CP_CLMP_EN AGC_MODE_MAN CP_MODE_GAIN_ADJ[7:0] 13-bit signed 13-bit signed GAIN_MAN 8-bit A_GAIN[9:0]/B_GAIN[9:0]/C_GAIN[9:0] PREGAIN GAIN agc-gain 10-bit 10-bit 10-bit...
Page 258: Sync Processed By Cp Section
9.6.1 The ADV7850 has two sync slicers. Each sync slicer can slice one of the four possible embedded sync signals: SYNC1, SYNC 2, SYNC 3 and SYNC 4. The sliced signals are output on the internal sliced signals, EMB_SYNC_SEL1 and EMB_SYNC_SEL2 (see ain_sel[2:0]).
Page 259: External Sync And Sync From Hdmi Section
9.6.2.1 Signals Routing to Synchronization Channels The ADV7850 has two synchronization channels. Each channel consists of one SSPD and one STDI section. When an HDMI input is applied, the HDMI core will generate HSync, VSync, and DE signals and supply them as input to each synchronization channel shown in Figure 86.
Page 260: Xtal Clock Registering And Glitch Rejection Filter
ADV7850 Two muxes are used to select HSync /CSync 1 and HSync /CSync 2 from the three possible HSync signals. Similarly, two muxes are used to select VSync 1 and VSync 2 from the three possible VS signals. These muxes are controlled by sync_ch1_hs_sel[1:0], sync_ch1_vs_sel[1:0], sync_ch2_hs_sel[1:0], and sync_ch2_vs_sel[1:0].
Page 261: Signal Routed To Sspd Blocks
ADV7850 each input. Each output has two instances, one with the same name as the input, and one with _GR at the end of the name. The _GR signals are latched by the XTAL clock and have a digital filter applied to them, whereas the output signals with the same name as the input signals are true bypass versions of the input signals;...
Page 262: Final Sync Muxing Stage
TO CP CORE FILTER Figure 87: Final Sync Muxing Stage 9.7 SYNCHRONIZATION PROCESSING CHANNEL MUX The ADV7850 has two synchronization processing channels, as shown in Figure 86. These contain SSPD and the STDI functionality that receives synchronization, as described in Section 9.6.2.1.
Page 263: Synchronization Source Polarity Detector
ADV7850 sync_ch_auto_mode, IO, Address 0x07[7] This control is used to set automatic synchronization channel selection to the CP core. Auto mode selects which synchronization channel drives the CP based on the free run status of each channel. The priority of selection is determined by SYNC_CH1_PRIORITY when both channels are in free run mode.
Page 264: Figure 88: Sspd Auto Detection Flowchart
ADV7850 The ADV7850, by default, tries to use separate HSync/VSync signals even if there are embedded sync signals also available. The user can change this behavior by using ch1_sspd_pp_en and ch2_sspd_pp_en. By enabling these registers, the first preference for SSPD will be the...
Page 265 ADV7850 ch2_sspd_cont, Addr 44 (CP), Address 0x41[1] This control is used to set the synchronization source polarity detection mode for sync channel 2 SSPD. Function ch2_sspd_cont Description Sync channel 2 SSPD works in one-shot mode (triggered by a 0 to 1 transition on ch2_trig_sspd bit) 1 ...
Page 266 ADV7850 Function ch1_pol_man_en Description 0  Use result from sync channel 1 SSPD polarity autodetection Manual override, use ch1_pol_vs and ch1_pol_hs ch2_pol_man_en, Addr 44 (CP), Address 0x41[7] This control is used to override the polarity detection by sync channel 2 SSPD.
Page 267: Sspd Readback Signals
ADV7850 emb_sync_on_all, Addr 44 (CP), Address 0x67[5] This control is used to alter the gain computed by the AGC based on the presence of an embedded synchronization on channels A, B and C. It is used only in the case of RGB input and RGB output with color controls enabled.
Page 268 ADV7850 Function ch2_sspd_dvalid Description 0  Sync channel 2 SSPD results not valid for readback Sync channel 2 SSPD results valid (detection finished) ch1_cur_sync_src[1:0], Addr 44 (CP), Address 0xB5[1:0] (Read Only) This readback displays the current synchronization source detected by sync channel 1 SSPD.
Page 269 ADV7850 • ch1_hs_act is set to 1 if the SSPD has detected eight edges or four periods on the HSync signal • ch1_hs_act is set to 0 if the SSPD has detected less than eight edges or four periods on the HSync signal ch2_hs_act, Addr 44 (CP), Address 0x4F[4] (Read Only) This readback displays activity on the HSync/CSync input to sync channel 2 SSPD.
Page 270: Figure 89: Sspd Vsync And Hsync Monitoring Operation
ADV7850 Function ch2_vs_act Description 0  No activity detected on VSync input to sync channel 2 SSPD VSync input to sync channel 2 SSPD carries an active signal The SSPD section continuously monitors the VSync input signal over timing windows of 2...
Page 271: Standard Detection And Identification
ADV7850 Function sspd_rslt_chngd_ch1_st Description 0  No SSPD result changed for sync channel 1 interrupt event occurred SSPD result changed for sync channel 1 interrupt event occurred sspd_rslt_chngd_ch1_raw, IO, Address 0x5B[0] (Read Only) Status of the SSPD Result Changed on sync channel 1 interrupt signal. When set to 1 it indicates a change in SSPD result of the currently selected sync channel.
Page 272 The four parameters should only be read after the chx_stdi_dvalid flag has gone high for the continuous/single shot mode. In real-time continuous mode, the ADV7850 allows the user to monitor the real-time timing measurement regardless of the chx_stdi_dvalid flag.
Page 273 ADV7850 bypass_stdi1_locking, Addr 44 (CP), Address 0xF5[1] This control is used to bypass STDI locking for sync channel 1. Function bypass_stdi1_locking Description 0  Update ch1_bl, ch1_lcf and ch1_lcvs. Only sync channel 1 STDI locks and ch1_stdi_dvalid set to 1.
Page 274: Detailed Mechanism Of Stdi Block Horizontal/Vertical Lock Mechanism
ADV7850 ch2_sdti_dvalid is set to 1 only after four fields with the same length are recorded. As a result, STDI measurements can take up to five fields to finish. Function ch2_stdi_dvalid Description 0  Sync channel 2 STDI measurement not valid...
Page 275: Figure 92: Stdi Vertical Locking Operation
ADV7850 Field2– Field3 ≦threshold? Field2– Field3 ≦threshold? Field4 – Field5 ≦threshold? Field4 – Field5 ≦threshold? Field1 – Field2 ≦threshold? Field1 – Field2 ≦threshold? Field3 – Field4 ≦threshold? Field3 – Field4 ≦threshold? Field2 Field2 Field3 Field3 Field4 Field4 Field1 Field1 Field6...
Page 276 ADV7850 Function ch1_lcvs[4:0] Description xxxxx Readback value ch2_lcvs[4:0], Addr 44 (CP), Address 0x4B[7:3] (Read Only) This readback displays the sync channel 2 line count in a VSync. It displays the number of lines in a VSync period measured on sync channel 2.
Page 277: Stdi Usage
ADV7850 Function ch1_stdi_intlcd Description 0  Indicates video signal on sync channel 1 with non interlaced timing Indicates signal on sync channel 1 with interlaced timing ch2_stdi_intlcd, Addr 44 (CP), Address 0x49[6] (Read Only) This readback displays interlaced versus progressive mode detected by sync channel 2 STDI. The readback is valid if ch2_stdi_dvalid is set to 1.
Page 278: Stdi Readback Values For Graphics Standards
As shown in Figure 95, the ADV7850 CP can output the following three primary and two secondary synchronization signals, which are controlled by the output control block in the CP block. These timing signals are sent to the HDMI Tx section.
Page 279: Cp Primary Synchronization Signals
ADV7850 Secondary: • CS timing reference output shared with the HS pin • DE (indicates active region) shared with the FIELD pin The user can program the primary and secondary synchronization signals, repositioning them in order to control the display area, as...
Page 280: Hsync Timing Controls
ADV7850 All of these parameters are given as signed values. This means that rather than adjusting the absolute position of a signal, these adjustments allow the user to advance (negative value) or delay (positive value) the respective timing reference signals.
Page 281: Figure 97: Hs Timing
ADV7850 Figure 97: HSync Timing Rev. A May 2012...
Page 282 ADV7850 start_hs[9:0], Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0] This control is used to shift the position of the leading edge of the HSync output by the CP core. It stores a signed value in a twos complement format. This control is the number of pixel clocks by which the leading edge of the HSync is shifted (e.g. 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks towards the active video).
Page 283: Vsync Timing Controls
ADV7850 Examples of how to control the end of the HSync timing signal: end_hs[9:0] Result Note 0000000000  0x000 No move (default) sec shift later than default 0000000001 0x001 Minimum → 256 x sec shift later than default 0100000000 0x100...
Page 284 ADV7850 Examples of how to control the start of the VS timing signal: start_vs[3:0] Result Note 0000  No move (default) 0001 1 HSync shift later than default Minimum → 0011 3 HSync shift later than default 0111 7 HSync shift later than default Maximum →...
Page 285: De Timing Controls
ADV7850 end_vs[3:0] Result Note 0111 7 HSync shift later than default Maximum → 1111 1 HSync shift earlier than default Minimum ← 1101 3 HSync shift earlier than default 1000 8 HSync shift earlier than default Maximum ← Closer to start of active video...
Page 286 ADV7850 Function de_v_end[5:0] Description 100000 -32 lines of shift 1111 11 -1 line of shift 000000  Default 000001 +1 line of shift 011111 +31 lines of shift de_v_start_even[5:0], Addr 44 (CP), Address 0x87[5:0] This control is used to vary the start position of the VBI region in an even field. It stores a signed value represented in a twos complement format.
Page 287: Field Timing Controls
ADV7850 de_v_start_even_r[3:0], Addr 44 (CP), Address 0x31[7:4] This control is used to vary the position of the start of the extra VBI region between L and R fields during the even field in the field alternative packing in 3D TV video format through HDMI. It stores a signed value represented in a twos complement format. The unit of de_v_end_even[9:0] is one line.
Page 288 ADV7850 start_fe[3:0] Result Note 1111 1 HSync shift earlier than default Minimum ← 1101 3 HSync shift earlier than default 1000 8 HSync shift earlier than default Maximum ← Closer to active video Away from active video start_fo[3:0], Addr 44 (CP), Address 0x80[3:0] This control is used to shift the position of the start of the odd field edge of the FIELD signal output by the CP core.
Page 289: Figure 98: 525I Vs Timing
ADV7850 Figure 98: 525i VS Timing Rev. A May 2012...
Page 290: Figure 99: 625I Vs Timing
ADV7850 Figure 99: 625i VS Timing Rev. A May 2012...
Page 291: Figure 100: 525P Vs Timing
ADV7850 Figure 100: 525p VS Timing Rev. A May 2012...
Page 292: Figure 101: 625P Vs Timing
ADV7850 Figure 101: 625p VS Timing Rev. A May 2012...
Page 293: Figure 102: 720P Vs Timing
ADV7850 Figure 102: 720p VS Timing Rev. A May 2012...
Page 294: Figure 103: 1080I Vs Timing
ADV7850 Figure 103: 1080i VS Timing Rev. A May 2012...
Page 295: Figure 104: 1080P Vs Timing
ADV7850 Figure 104: 1080p VS Timing Rev. A May 2012...
Page 296: Hcount Timing Control
Default 9.9 CP DATA PROCESSING DELAY CONTROLS The ADV7850 provides controls to delay data by 1 pixel after CP CSC. dly_a, Addr 44 (CP), Address 0xBE[7] This control is used to delay the data on channel A by one pixel clock cycle.
Page 297: Figure 105: Synchronization Lock Robustness Measurement
ADV7850 video signal HS detection threshold as per ISD_THR[7:0] ISD[8:0] value represents area value Figure 105: Synchronization Lock Robustness Measurement The measurements are performed on a line-by-line basis on all video lines but not during the VBI. For video lines during the VBI, the result of the last active video line is kept.
Page 298: Noise And Calibration
NOISE AND CALIBRATION The ADV7850 provides hardware for a noise and calibration measurements. The two measurements share some hardware control (window). However, they are different in the way they examine the input data. The measurements are executed during a time window.
Page 299: Calibration Measurement
C register CALIB[10:0]. The number format is signed with a possible range of -1024 to +1024. It is envisaged to provide the ADV7850 with a flat gray field and to position the window in the middle of active video for a meaningful measurement.
Page 300 ADV7850 Function ch1_f_run_thr[2:0] Description Minimum difference to switch into free run is 2. Maximum difference to switch out of free run is 1. Minimum difference to switch into free run is 256. Maximum difference to switch out of free run is 200.
Page 301: Vertical Run Conditions
ADV7850 Function ch2_fr_ll[10:0] Description 0x000  Actually used internal free run line length decoded from prim_mode[3:0] and vid_std[5:0]. All other values Number of crystal clocks in ideal line length. Used to enter or exit free run mode. Notes: This parameter has no effect on the video decoding.
Page 302 ADV7850 Function ch2_fl_fr_threshold[2:0] Description Minimum difference to switch into free run is 36 lines. Maximum difference to switch out of free run is 31 lines. Minimum difference to switch into free run is 18 lines. Maximum difference to switch out of free run is 15 lines.
Page 303: Free Run Default Color Output
9.12.3 In the event of loss of input signal, the ADV7850 may enter free run and can be configured to output a color rather than noise. By default, the ADV7850 is configured to output a blue screen. The default color values are provided in...
Page 304: Cp Status
ADV7850 cp_def_col_auto, Addr 44 (CP), Address 0xBF[1] This control is used to enable the insertion of the default color when the CP free runs. Function cp_def_col_auto Description Disable automatic insertion of default color 1  Output default colors when CP free runs cp_def_col_man_val, Addr 44 (CP), Address 0xBF[2] This control is used to enable the manual selection of the color used when the CP core free runs.
Page 305: Auto Graphics Mode
This bit must be set to allow a user programmable PLL divide ratio to be used. • pll_div_ratio[12:0] The PLL divide ratio is equal to the number of samples per line. The ADV7850 multiplies the incoming HSync frequency by the PLL divide ratio to generate the sampling clock. •...
Page 306 ADV7850 ch1_fr_ll[10:0]/ch2_fr_ll[10:0] specifies the expected line length of the incoming video. If the actual line length is different from the expected line length by more than a programmable threshold, the decoder will free run. • cp_lcount_max[11:0]/ch2_fr_field_length[11:0] interlaced cp_lcount_max[11:0] ch2_fr_field_length[11:0] specify the expected number of lines per frame. If the actual number of lines per frame is different from the expected number by more than a programmable threshold, the decoder will free run.
Page 307 ADV7850 Function cp_end_vbi_even[11:0] Description 0x000 << Default value The following controls are intended only for use with HDMI 3D standards. cp_start_vbi_r[11:0], Addr 44 (CP), Address 0x2A[7:0]; Address 0x2B[7:4] This control is used to manually set the value for the start position of the VBI region. This is the extra blank region preceding the odd right (R) field in the 3D TV field alternative packing format supported by HDMI.
Page 308: Graphics Controls
ADV7850 cp_end_hs[12:0], Addr 44 (CP), Address 0x24[4:0]; Address 0x25[7:0] This control is used to set the position of the end of the HSync output signal in the CP core in autographics mode only. Programming of this control is optional and should only be performed when the part is set in autographics mode. The value is unsigned.
Page 309 ADV7850 ignr_clmp_vs_mar_start[4:0], Addr 44 (CP), Address 0x8A[0]; Address 0x8B[7:4] This control is used to set the start of the window during which the clamp is ignored. It stores the unsigned number of pixel clocks between the start position of the window relative to the leading edge of the VSync. This control should only be used if vid_std[5:0] is set for autographics mode.
Page 310: Vbi Data Processor
ADV7850 10 VBI DATA PROCESSOR The VBI Data Processor (VDP) is capable of processing multiple VBI data standards on analog video. For low data rate VBI standards like Closed Captioning (CCAP), Wide Screen Signaling (WSS), or Copy Generation Management System (CGMS), the user can read the decoded data bytes from dedicated I C registers for different standards.
Page 311: Table 62: Vbi_Data_Std[3:0] Values Corresponding To A Particular Vbi Standard
ADV7850 Table 62: vbi_data_std[3:0] Values Corresponding to a Particular VBI Standard vbi_data_std[3:0] 625/50 – PAL 525/60 – NTSC 525p 625p 720p 1080i (Interlaced) (Interlaced) Binary Dec 0001 Teletext system Teletext system Reserved Reserved Reserved Reserved 0010 Reserved Reserved Reserved Reserved...
Page 312: Vdp Manual Configuration
ADV7850 525i 625i 525p 625p 720p 1080i Line Default Line Default Line Default Line default Line Default Line Default vbi_data_st vbi_data_ vbi_data_std vbi_data_std vbi_data_std vbi_data_std [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] VDP Manual Configuration 10.1.2 Table 63 shows default standards decoded by the VDP. However decoded standard(s) on specific line(s) can be manually reconfigured by...
Page 313: Teletext System Identification
ADV7850 Register Line Numbers in which VBI Data is Inserted Location Control Names 525i 625i 1080i 525p, 625p, 720p vdp_man_line_16_36[7:4] 0x73 21 + Full Field vdp_man_line_17_37[7:4] 0x74 vdp_man_line_18_38[7:4] 0x75 vdp_man_line_19_39[7:4] 0x76 vdp_man_line_20_40[7:4] 0x77 25 + Full Field 25 + Full Field...
Page 314: Vdp Decoded Data Readback Registers
ADV7850 Function vdp_ttxt_type_man_en Description 0  Manual programming of teletext disabled Manual programming of teletext enabled vdp_ttxt_type[1:0], Addr 48 (VDP), Address 0x60[1:0] This readback indicates the teletext type detected. It is functional only if vdp_ttxt_type_man_en is set to 1. Function...
Page 315: Closed Captioning Readback Registers
ADV7850 Function vdp_status_wss_cgms Description 0  WSS or CGMS type A data not detected WSS or CGMS type A data detected vdp_cgms_wss_data[23:0], Addr 48 (VDP), Address 0x43[7:0]; Address 0x44[7:0]; Address 0x45[7:0] (Read Only) This readback displays decoded data for CGMS type A and WSS.
Page 316: Vitc Readback Registers
ADV7850 vdp_status_ccap, Addr 48 (VDP), Address 0x40[0] (Read Only) This readback displays the closed caption data detection status. Function vdp_status_ccap Description 0  Closed caption data not detected Closed caption data detected vdp_status_ccap_even_field, Addr 48 (VDP), Address 0x40[1] (Read Only) This readback displays the closed caption data in the even field status.
Page 317: Vps, Pdc, Utc, Gemstar And Cgms Type B Readback Registers
ADV7850 status_clear_vitc, Addr 48 (VDP), Address 0x78[6] (Self-Clearing) This control is used to refresh the VITC status registers. This is a self-clearing bit. Function status_clear_vitc Description 0  Do not refresh VITC status registers Refresh VITC status registers vdp_vitc_calc_crc[7:0], Addr 48 (VDP), Address 0x5E[7:0] (Read Only) This readback indicates the calculated CRC value for decoded VITC data.
Page 318: Table 67: Vdp_Gs_Vps_Pdc_Utc_Cgmstb_Data Readback Registers
ADV7850 gs_vps_pdc_utc_cgmstb[2:0], Addr 48 (VDP), Address 0x9C[2:0] The readback registers for VPS, PDC, UTC and CGMS type B are shared. This control is used to identify which type of data is to be written to the shared registers. Function gs_vps_pdc_utc_cgmst...
Page 319: Table 68: Cgms Type B Readback Registers
ADV7850 Gemstar The Gemstar decoded data is made available in the ancillary stream and through the fast I C port. For evaluation purposes only one line of Gemstar can be made available VDP readback registers. Gemstar must be selected via gs_vps_pdc_utc_cgmstb[2:0].
Page 320: Readback Registers
ADV7850 CGMS Type B Readback Registers VDP Map Address vdp_gs_vps_pdc_utc_cgmstb_data[31:24] 0x4A vdp_gs_vps_pdc_utc_cgmstb_data[39:32] 0x4B vdp_gs_vps_pdc_utc_cgmstb_data[47:40] 0x4C vdp_gs_vps_pdc_utc_cgmstb_data[55:48] 0x4D vdp_gs_vps_pdc_utc_cgmstb_data[63:56] 0x4E vdp_gs_vps_pdc_utc_cgmstb_data[71:64] 0x4F vdp_gs_vps_pdc_utc_cgmstb_data[79:72] 0x50 vdp_gs_vps_pdc_utc_cgmstb_data[87:80] 0x51 vdp_gs_vps_pdc_utc_cgmstb_data[95:88] 0x52 vdp_gs_vps_pdc_utc_cgmstb_data[103:96] 0x53 10.4 READBACK REGISTERS C readback registers have separate registers for CCAP, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. The details of these registers and their access procedure are described in Section 10.5.
Page 321: Content Based Data Update
The user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. For more information on using the VDP interrupts, refer to Section and the ADV7850 Software Manual. Rev. A May 2012...
Page 322: Spi Readback Registers
SPI Data Formats – Slave Mode 10.7.1 The ADV7850 will always be configured in SPI master mode when transferring to the ADV8003. However, the ADV7850 can also output VBI data over SPI in slave mode. The format of these packets is shown in...
Page 323: Table 71: Teletext Spi Slave Mode Output Format
Two bytes are sent that are not transmitted when the ADV7850 SPI Tx is in master mode. These are the dummy byte and the byte indicating more data in the FIFO. More data in FIFO: Because of being in slave mode, the ADV7850 must indicate to the master that there is more data to read. Hence, it transmits: •...
Page 324: Spi Data Formats - Master Mode
No more data in FIFO SPI Data Formats – Master Mode 10.7.2 In master mode, the ADV7850 outputs the data according to the ancillary data packet format. The format for ancillary data packets is shown in Table 76 (considering 8-bit (byte) ancillary data only).
Page 325: Table 77: Number Of Bits In Each Of Framing Codes
ADV7850 User Data Word N-1 VBI Word N-1[7:0] Padding �� 6 Padding Checksum Checksum Ancillary packet data is composed of the following: • Ancillary Data Preamble: First 3 bytes are the ancillary data preamble which indicates the start of a data packet. It will always be 0x00, 0xFF, 0xFF.
Page 326: Configuring Master Mode On The Spi Port
In the VDP Map (0x48), set Register 0x62 to 0x95. This control inserts the decoded VBI data into the ancillary data stream. • In the IO Map (0x40), set Register 0x1E to 0x7E. This control ensures the VBI SPI Tx on the ADV7850 is set as the master since the SPI Rx on the ADV8003 is always a slave.
Page 327 ADV7850 Function enable_vdp_data_over Description _spi 0 << VDP FIFO is not cleared by SPI logic VDP FIFO fast registers are cleared when one byte read. spi_slave_in_burst_mode, IO, Address 0x1E[5] This is valid when SPI is in slave mode. Function spi_slave_in_burst_mo...
Page 328: Spi Vdp Controls And Readbacks
ADV7850 Function vdp_data_packet_size[ Description 5:0] 111111  default value chip_select_polarity, IO, Address 0xE4[2] A control to decide polarity of the chip select for SPI during slave configuration. Function chip_select_polarity Description 0 << Active low Active high clock_polarity, IO, Address 0xE4[1] A control to adjust the clock polarity for the SPI Interface(CPOL).
Page 329 ADV7850 Function vdp_fast_vbi_std[3:0] Description 0001 Teletext 0010 0011 VITC 0100 WSS/CGMS type A 0101 Gemstar 1X 0110 Gemstar 2X 0111 CCAP 1000 CGMS type B 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Custom 1 1110 Custom 2 1111...
Page 330: Adv7850 Vdp Interrupt Generation
10.7.5 The ADV7850 generates a VBI data interrupt when the VBI data is received and when the line counter reaches a predetermined value. This ensures that only one VBI data interrupt can occur once per field, regardless of which lines the VBI data is on, and regardless if the VBI data is on concurrent lines or not.
Page 331: Figure 111: Vdp Interrupt Operation
128 bytes SOC starts additional block read of 128 bytes by keeping Chip Select low and continuing to clock data out of ADV7850. SOC interrogates previous block of 128 bytes. Was FIFO_STATUS nibble set to 0xFX in...
Page 332 ADV7850 Byte No Contents Description TTXT Data Byte 41 0x00 Framing Code 0x00 Framing Code 0x27 Framing Code 0xFX More data in FIFO 0x2F Number of bytes in this block (= 47) VBI standard and field information TTXT Data Byte 0...
Page 333: Audio Codec
AUDIO CODEC OVERVIEW The ADV7850 supports an audio CODEC comprising a stereo ADC and a stereo DAC. A 5:1 stereo mux is located in front of the ADC input. The DAC output is available as a line level output, and is also passed through an internal headphone amplifier. The integrated headphone amplifier eliminates the need for an external amplifier when driving headphones.
Page 334: Analog Audio Adc Input Selection
Using these controls, it is also possible to achieve mono in to stereo out functionality. The audio mux output is enabled using muxout_en. The ADV7850 audio codec provides a stereo output mux. The mux output hardware configuration is shown in Figure 115.
Page 335: Analog Audio Mux Input/Mux Output Configuration Overview
11.2.3 The ADV7850 is designed to use a combination of internal and external resistances. Measured from the system audio input connector, the total nominal input impedance is 32.1 kΩ. All system audio inputs are designed to support 2.8 V rms audio input.
Page 336: Audio Codec Functionality
ADV7850 Note: The analog audio input pins of the ADV7850 only see 880 mV RMS signals. However, the ADV7850 incorporates a gain stage to restore the mux output level to 1.0 V rms. An external line driver is required to restore the audio output signals to the SCART specification of 2.8 V rms.
Page 337: Vref_Audio, Filta And Filtd (Location)
ADV7850 Figure 117: Audio PLL Loop Filter Components pll_ref_freq[1:0], Addr 5C (audio_codec), Address 0x00[7:6] This control is used to select the PLL reference input frequency. Function pll_ref_freq[1:0] Description 00  512*Fs (24.576 MHz) 256*Fs (12.288 MHz) 128*Fs (6.144 MHz) 64*Fs (3.072 MHz)
Page 338: Dac And Headphone Outputs
11.3.3 The ADV7850 has an audio DAC output and a headphone output. The stereo DAC output is available as a line level output, and is also passed through an internal headphone amplifier. The integrated headphone amplifier eliminates the need for an external amplifier when driving headphones.
Page 339: Figure 120: Audio Codec Headphone Output Hardware Configuration
ADV7850 capacitors. Figure 120: Audio Codec Headphone Output Hardware Configuration To use the headphone output, the left and right headphone amplifiers must be powered up using hp_left_amp_pu and hp_right_amp_pu. The HPOUT_L and HPOUT_R pins are tristated by default. When the headphone output is in use, this tristate condition must be...
Page 340: Volume Controls
ADV7850 hp1_atten[4:0], Addr 5C (audio_codec), Address 0x06[4:0] This control is used to set headphone amplifier attenuation (0 dB to -46.5 dB in -1.5 dB steps). Function hp1_atten[4:0] Description 00000  0dB ... hp_scp, Addr 5C (audio_codec), Address 0x05[3] This control is used to enable short circuit protection.
Page 341: Audio Power Up/Down Controls
ADV7850 11.4 AUDIO POWER UP/DOWN CONTROLS The audio Codec includes power up and power down controls. eng_dig_pu, Addr 5C (audio_codec), Address 0x01[3] This control is used to power up the digital engine. Function eng_dig_pu Description 0  Power down digital engine...
Page 342 ADV7850 Function dac_ana_stdby_dis Description DACs in standby mode 1  DACs in normal mode left_dac_1_ana_stdby, Addr 5C (audio_codec), Address 0x09[0] This control is used to set the DAC left channel into standby mode. Function left_dac_1_ana_stdby Description 0  Full power...
Page 343 ADV7850 Function right_adc_1_pu Description 0  Power down ADC right channel Power up ADC right channel hp_left_amp_pu, Addr 5C (audio_codec), Address 0x05[4] This control is used to power up the headphone left amplifier. Function hp_left_amp_pu Description 0  Power down headphone left amplifier...
Page 344: Memory Controller
12.1 MEMORY REQUIREMENTS The ADV7850 supports a DDR2 memory interface. Depending on the feature required, the appropriate memory device can be selected. The external memory is required for 3D comb and Frame TBC operation only. The ADV7850 requires the following memory specifications: •...
Page 345: Drive Strength Controls
Output DRIVE STRENGTH CONTROLS 12.3 The drive strength of signals from the ADV7850 memory interface can be configured with the following controls. The clock and the DQS outputs have independent drive strength controls. dqs_drv_str[7:0], XMEM_GAMMA, Address 0x39[7:0] This control is used to adjust the drive strength setting for the upper DQS outputs to the DDR2 memory.
Page 346: Figure 121: Ddr2 Bist Test Architecture
ADV7850 32-bit Data Address Address DDR2 Loopback 512M x 16 Controller Control Test Logic Control External DDR2 Memory 16-bit Data 32-bit Data Figure 121: DDR2 BIST Test Architecture A DDR2 BIST test is initialized and started via the following writes:...
Page 347: External Memory Layout Guidelines
12.5 EXTERNAL MEMORY LAYOUT GUIDELINES The ADV7850 should be placed as close to and on the same side as the external DDR2 memories. Balanced T-routing should be used for all shared connections between the ADV7850 and the external DDR2 memories.
Page 348 The DDR2 reference voltage (DDR_VREF) should be routed as far away as possible from other the signals to avoid any variations in the voltage. This trace should be wide. There should be a 100 nF decoupling cap close to the DDR2 reference voltage pins as well as the ADV7850 reference pin. Rev. A May 2012...
Page 349: Hdmi Transmitter
ADV7850 interrupts). The ADV7850 also features a status bit, rx_sense, which can be used to detect the presence of TMDS clock terminations from the sink. If the ADV7850 detects a voltage level higher than 1.8 V on the clock lines of its TMDS output port,...
Page 350: Hdmi Dvi Selection
13.3 HDMI DVI SELECTION The HDMI Tx core supports the transmission of both HDMI and DVI streams. The type of stream the ADV7850 transmits is set via hdmi_mode_sel. In DVI transmission mode, no packets will be sent and all registers relating to packets and InfoFrames will be disregarded.
Page 351: Av Mute
13.5 TX SQUELCH FEATURE The ADV7850 provides a squelch feature to mute the video clock when there is no input connected to the HDMI Input. This feature ensures that no spurious clocks signals are output to the backend device when a cable is disconnected or an input source switches off.
Page 352: Source Product Description Infoframe
ADV7850 video_clock_detect, Addr B8 (Main), Address 0xEF[2] This control is used to enable the HDMI Tx Squelch feature. This should be set to 0 in all analog input modes. Function video_clock_detect Description Disable TMDS Clock detection (and HSync activity Detect) 0 ...
Page 353: Spare Packets
SPD Data Byte 27 13.7 SPARE PACKETS The user can configure the ADV7850 to send any type of packets or InfoFrames via the spare packets controls and associated configuration registers. The ADV7850 features two such spare packets that can be enabled via the...
Page 354: System Monitoring
Spare Packet Data Byte 27 13.8 SYSTEM MONITORING General Status and Interrupts 13.8.1 The ADV7850 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt and status are listed in Table Table...
Page 355: Edid/Hdcp Controller Status
13.10 EDID/HDCP CONTROLLER ERROR CODES If an HDCP authentication occurs between the ADV7850 and the downstream sink, the ADV7850 can trigger an interrupt to notify this error to the user or the controlling CPU. The EDID/HDCP controller will then report the HDCP error code via the...
Page 356: Video Setup
13.11.1 The HDMI Tx core of the ADV7850 receives video data from the ADV7850 digital core via a 36-bit wide bus and four synchronization signals; the pixel clock, the data enable, the horizontal and the vertical synchronization signals. The HDMI Tx core always receives the video data in a 4:4:4 and SDR format.
Page 357: Pixel Repetition
Pixel repetition is used in HDMI to increase the amount of blanking period available to send packets or to increase the pixel clock to meet the minimum TMDS clock rate of 25 MHz. The ADV7850 offers three choices for the user to implement pixel repetition in the Tx core.
Page 358: Video Related Packets And Infoframes
ADV7850 must be programmed in ext_target_pr[1:0]. Refer to the latest HDMI specification for more details on valid pixel repetition formats. Max mode: Max mode works in the same way as automatic mode, except that it always selects the highest pixel repetition factor the Tx core is capable of.
Page 359: Mpeg Infoframe
The MPEG InfoFrame is defined in the latest CEA 861 specification. Currently, the specification does not recommend using this InfoFrame. The transmission of MPEG InfoFrames can be enabled by setting mpeg_pkt_en. When the transmission of MPEG InfoFrames is enabled, the ADV7850 transmits an MPEG InfoFrame once every two video fields. Table 90 provides a list of registers that can be used to configure MPEG InfoFrames.
Page 360: Gamut Metadata
When the transmission of GMP is enabled, the ADV7850 transmits a GMP once every two video fields. The ADV7850 transmits the GMP data starting 400 pixel clock cycles after the leading edge of VSync. In order to avoid corrupting the GMP data during transmission, it is recommended that the user synchronizes all I C writes to the GMP registers so that the write begins 512 pixel clock cycles after the VSync leading edge.
Page 361: Figure 124: I C Write Timing If Gmp Data
ADV7850 Function gm_pkt_en Description 0  Disable gamut metadata packet Enable gamut metadata packet Falling edge of last DE of last field Rising edge of first DE of next field VSync GMP sending window 400 pixel 112 pixel Initiate I2C...
Page 362: Audio Setup
ADV7850 13.12 AUDIO SETUP Input Format 13.12.1 The ADV7850 is capable of receiving audio data in I2S, SPDIF, DSD or High Bit Rate (HBR) formats for packetization and transmission over the HDMI output interface. audio_sel[2:0], audio_mode[1:0] i2sformat[1:0] must be used to configure the Tx core according to the incoming audio input.
Page 363: I2S Audio
13.12.2 I2S Audio The ADV7850 can accommodate the reception of up to four stereo channels of I2S audio at up to a 192 kHz sampling rate. The number of I2S channels the Tx processes can be selected with audioif_cc[2:0]. The selection of the active I2S channels is done via i2senable[3:0]. The audio sampling frequency of the input stream must be set appropriately via i2s_sf[3:0].
Page 364 The ADV7850 also supports the reception of an I2S stream in both 64-bit and 32-bit modes, so either 32- or 16- bit clock (that is, the signal input through SCLK pin) edges or cycles per channel are valid. The ADV7850 will adapt to 32- or 64-bit modes automatically, and the current mode can be read in i2s_32bit_mode.
Page 365 ADV7850 Function audioif_cc[2:0] Description 000  Refer to stream header 2 channels 3 channels 4 channels 5 channels 6 channels 7 channels 8 channels i2senable[3:0], Addr B8 (Main), Address 0x0C[5:2] This control is used to enable the I2S pins. Function...
Page 366 ADV7850 Function subpkt0_r_src[2:0] Description 001  Default subpkt1_l_src[2:0], Addr B8 (Main), Address 0x0F[5:3] This control is used to specify the source of the sub packet 1, left channel. Function subpkt1_l_src[2:0] Description 010  Default subpkt1_r_src[2:0], Addr B8 (Main), Address 0x0F[2:0] This control is used to specify the source of the sub packet 1, right channel.
Page 367: Figure 125: Iec60958 Sub Stream
User Data Channel Status Block Start Flag Figure 126: AES3 Stream Format Input to ADV7850 LRCLK LEFT RIGHT SCLK DATA 32 Clock Slots 32 Clock Slots Figure 127: Timing of Standard I2S Stream Input to ADV7850 Rev. A May 2012...
Page 368: Spdif Audio
SPDIF stream and must be programmed in i2s_sf[3:0]. Note that the sampling frequency that is used in the Audio Sample packets sent to the downstream sink can be read from spdif_sf[3:0]. The ADV7850 is capable of accepting SPDIF with or without an audio master clock input on the MCLK pin. When the ADV7850 does Rev. A May 2012...
Page 369: Dsd Audio
ADV7850 not receive an audio master clock, the ADV7850 uses the bit clock input via the SCLK pin to internally generate an audio master clock and determine the CTS value. spdif_sf[3:0], Addr B8 (Main), Address 0x04[7:4] (Read Only) This readback displays the SPDIF audio sampling frequency decoded by the hardware.
Page 370: N And Cts Parameters
HBR stream input to a non ADI HDMI receiver device. Refer to Table 93 for additional details on the HBR modes supported by the ADV7850. papb_sync, Addr B8 (Main), Address 0x47[6] For HBR audio this synchronizes the Pa and Pb syncwords with subpacket 0.
Page 371: N Parameter
The result can be read from cts_internal. Automatic mode is good for incoherent audio or video, where there is no simple integer ratio between the audio and video clock. The 20-bit N value used by the Tx core of the ADV7850 can be programmed in the field N. cts_sel, Addr B8 (Main), Address 0x0A[7] This control is used to select the CTS option;...
Page 372: Table 95: Recommended N And Expected Cts Values For 32 Khz Audio
ADV7850 Function cts_sel Description 0  Internally generated Set by user cts_manual[19:0], Addr 72 (Main), Address 0x07[3:0]; Address 0x08[7:0]; Address 0x09[7:0] Cycle Time Stamp (CTS) manually set. This parameter is used with the N parameter to regenerate the audio clock in the receiver.
Page 373: Audio Sample Packets
Audio Sample packets sent across the HDMI link to the downstream sink and corresponding ADV7850 fields located in the Tx Main register map. Note that the mapping shown in...
Page 374 ADV7850 Function audioif_ca[7:0] Description 00000000  Default cr_bit, Addr B8 (Main), Address 0x12[5] This control is used to set the copyright protection. Function cr_bit Description 0  Copyright Not copyright protected a_info[2:0], Addr B8 (Main), Address 0x12[4:2] This control is used to select the pre-emphasis on the audio output channels. Refer to IEC 60958 for more details.
Page 375: Table 98: I 2 S Channel Status Adv7850 Register Map Location Of Fixed Value
This control is used to set the channel status bits[0] and [1]. Bit 0 = 0 indicates consumer use. Bit 1 = 0 indicates LPCM audio. Function cs_bit_1_0[1:0] Description 00  Default Table 98: I S Channel Status ADV7850 Register Map Location of Fixed Value Channel Status Channel Status Bit Name Main Map Bit Main Map Bit Name or Fixed Value Consumer use...
Page 376 ADV7850 Channel Status Channel Status Bit Name Main Map Bit Main Map Bit Name or Fixed Value Channel number Figure 133 Figure 133 Channel number Figure 133 Figure 133 Channel number Figure 133 Figure 133 Sampling frequency 0x15[4] i2s_sf[0] Sampling frequency...
Page 377: Audio Infoframe
The ADV7850 can be configured to transmit audio InfoFrame by setting audioif_pkt_en to 1. When the transmission of audio InfoFrame is enabled, the ADV7850 transmits an audio InfoFrame once every two video fields. Table 99 provides a list of the registers that can be used to configure audio InfoFrames.
Page 378: Audio Content Protection Packet
100. The user can enable the transmission of an ACP packet to the downstream sink by setting acp_pkt_en to 1. When the transmission of ACP packets is enabled, the ADV7850 transmits an APC packets once every two video fields. acp_pkt_en, Addr B8 (Main), Address 0x40[4] This control is used to enable an ACP packet.
Page 379: Isrc Packet
The ADV7850 can be configured to transmit ISRC packet by setting isrc_pkt_en to 1. When the transmission of an ISRC packet is enabled, the ADV7850 transmits an ISRC packet once every two video fields. Table 101 Table 102 provide a list of the registers that can be used to configure ISRC packets.
Page 380: Edid Handling
DDC lines, TX_DDC_SCL and TX_DDC_SDA. This EDID/HDCP controller begins buffering segment 0 of the downstream sink EDID once the sink hot plug detect (HPD) is detected and the Tx core of the ADV7850 is powered up. The system can request additional segments by programming the EDID segment pointer edid_segment[7:0].
Page 381: Edid Definitions
EDID storage device (that is, EEPROM, RAM, and so on). The ADV7850 is capable of accessing up to 256 segments from EDID of the sink as allowed by the EDID specification. By writing the desired segment number to edid_segment[7:0], the ADV7850 will automatically access the correct portion of the sink EDID over the Tx DDC lines and load the 256 bytes into the EDID/HDCP memory.
Page 382: Edid_Tries Control
0. This could be used if a sink asserts high its HPD signal before the DDC bus is ready, resulting in several NACKs as the ADV7850 attempts to read the EDID. edid_trys[3:0], Addr B8 (Main), Address 0xC9[3:0] This control is used to set the maximum number of times that the EDID read will be attempted if unsuccessful.
Page 383 ADV7850 Function bksv_flag_intr Description 0 << Interrupt not active Interrupt active. The KSVs from the downstream sink have been read and available in the Memory Map hdcp_desired, Addr B8 (Main), Address 0xAF[7] This control is used to enable input A/V content encryption.
Page 384: Multiple Sinks And No Upstream Devices
13.14.2 When connecting the ADV7850 as a source to an HDMI input of a repeater, it is necessary to read all BKSVs from downstream devices. These BKSVs must be checked against a revocation list, which will be provided on the source content.
Page 385: Software Implementation
BKSV list read from the sink with the revocation list. Once the host controller has verified none of the BKSVs read from the sink are revoked, the ADV7850 can be configured to send content down to the sink.
Page 386: Av Mute
13.14.4 AV mute can be enabled once HDCP authentication is completed between the ADV7850 and the downstream sink. This can be used to maintain HDCP synchronization while changing video resolutions. While the KSVs for the downstream devices are being collected, an active HDCP link capable of sending encrypted video is established, but video should not be sent across the link until the KSVs have been Rev.
Page 387 Tx. It requests the function from the sink device. The best way to avoid sending unauthorized audio and video is to not send data to the Tx core of the ADV7850 until authentication between the ADV7850 and the downstream sink is complete.
Page 388: Register Access And Serial Ports Description
C PORT Register Access 14.1.1 The ADV7850 has fifteen 256-byte maps that can be accessed via the main I C ports, SDA and SCL. Each map has its own I C address and acts as a standard slave device on the I C bus.
Page 389: Protocol For Main I C Port
A logic 1 on the LSB of the first byte means that the master will read information from the peripheral. Each of the ADV7850 maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit.
Page 390: Ddc Port A
ADV7850 ADV7850 stores an address counter for each DDC port that maintains the value of the subaddress that was last accessed. The address counter is incremented by 1 every time a read or a write access is requested on the DDC port.
Page 391: Ddc Port C
ADV7850 DDC Port C 14.2.5 The DDC lines of the HDMI port C comprise the DDCC_SCL and DDCC_SDA pins. An HDMI host connected to the DDC port C accesses the internal E-EDID at address 0xA0 in read-only mode, and the HDCP registers at address 0x74 in read/write mode (refer to Figure 142).
Page 392: Interrupts
INTERRUPT ARCHITECTURE OVERVIEW The ADV7850 has a comprehensive set of interrupt registers located in the IO Map and the HDMI Tx Map. These interrupts can be used to indicate certain events in the HDMI Rx section, the CP, the SDP, and also the HDMI Tx.
Page 393: Interrupt Manual Assertion
ADV7850 intrq_op_sel[1:0], IO, Address 0x40[1:0] This control is used to configure an interrupt signal for INT1. Function intrq_op_sel[1:0] Description 00  Open drain Drive low when active Drive high when active Disabled intrq2_op_sel[1:0], IO, Address 0x41[1:0] This control is used to configure an interrupt signal for INT2.
Page 394: Multiple Interrupt Events
If an interrupt event occurs, and then a second interrupt event occurs before the system controller has cleared or masked the first interrupt event, the ADV7850 does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits as more than one may be active.
Page 395 ADV7850 of an edge event that happened in the past. This is the definition of an edge-sensitive raw bit. All raw bits, with the exceptions of intrq_raw and intrq2_raw, have corresponding status bits. The status bits always work in the same manner whether the raw bit is edge or level-sensitive.
Page 396: Figure 144: Level And Edge-Sensitive Raw, Status And Interrupt Generation
ADV7850 Function avi_info_mb1 Description 0  Disable AVI InfoFrame detection interrupt for INT1 Enable AVI InfoFrame detection interrupt for INT1 avi_info_mb2, IO, Address 0x63[0] This control is used to set the INT2 interrupt mask for the AVI InfoFrame detection interrupt. When set, an AVI InfoFrame detection event causes avi_info_st to be set and an interrupt generated on INT2.
Page 397: Figure 145: Avi_Info_Raw And Avi_Info_St Timing
ADV7850 AVI infoFrame Detection Internal Flag No AVI AVI InfoFrame InfoFrame Detected Detected AVI_INFO_RAW AVI_INFO_ST AVI_INFO_CLR AVI_INFO_CLR set to 1 set to 1 Time taken by Time taken by the CPU to clear the CPU to clear AVI_INFO_ST AVI_INFO_ST Figure 145: AVI_INFO_RAW and AVI_INFO_ST Timing...
Page 398: Description Of Rx Interrupt Bits
DESCRIPTION OF RX INTERRUPT BITS This section lists all the raw bits in the IO Map of the ADV7850 by category, and states whether the bit is an edge- or level-sensitive bit. A basic explanation for each bit is provided in the software manual and/or in the corresponding section of this manual. For certain interrupts that require additional explanations, these are provided in the subsections of this section.
Page 399 ADV7850 • acp_pckt_raw • vs_info_raw • ms_info_raw • spd_info_raw • audio_info_raw • avi_info_raw • cs_data_valid_raw • internal_mute_raw • av_mute_raw • audio_ch_md_raw • hdmi_mode_raw • gen_ctl_pckt_raw • audio_c_pckt_raw • gamut_mdata_raw • tmdspll_lck_a_raw • tmdspll_lck_b_raw • tmdspll_lck_c_raw • tmdspll_lck_d_raw • tmds_clk_a_raw •...
Page 400: Additional Explanations
ADV7850 • audio_mode_chng_raw • parity_error_raw • new_samp_rt_raw • audio_flt_line_raw • new_tmds_frq_raw • fifo_near_uflo_raw • ms_inf_cks_err_raw • spd_inf_cks_err_raw • aud_inf_cks_err_raw • avi_inf_cks_err_raw • aksv_update_a_raw • aksv_update_b_raw • aksv_update_c_raw • aksv_update_d_raw • bg_meas_done_raw • vs_inf_cks_err_raw • ri_expired_a_raw • ri_expired_b_raw • ri_expired_c_raw •...
Page 401: Figure 147: Suggested Method Of Handling Afe_Interrupt
ADV7850 START (AFE_INTERRUPT received) Set variable “X” = 1 Read TRIX_INT_STATUS[1:0] TRIX_INT_STATUS[1:0] =0b00 ? Interrupt on TRIX Read TRIX_READBACK[1:0] to determine current status of No interrupt on TRIX TRIX input and perform appropriate action Increment variable “X” X = 9 ?
Page 402: Stdi_Data_Valid_Raw
ADV7850 stdi_data_valid_raw 15.5.2 stdi_data_valid_raw is programmable as either an edge-sensitive bit or a level-sensitive bit using stdi_data_valid_edge_sel. Note that this control also configures whether an interrupt is generated only on the rising edge of stdi_data_valid_raw, or on both edges. stdi_data_valid_edge_sel, IO, Address 0x41[4] This control is used to configure the functionality of the stdi_data_valid interrupt.
Page 403: Video 3D Detection
15.5.5 All HDMI interrupts have a set of conditions that must be taken into account for validation in the display firmware. When the ADV7850 interrupts the display controller for an HDMI interrupt, the host must check that all validity conditions for that interrupt are met before processing that interrupt.
Page 404: Storing Masked Interrupts
ADV7850 • VIDEO_PLL_LOCKED_RAW is set to 1 Table 107: HDMI Interrupts Group 3 Interrupts isrc2_pckt isrc1_pckt acp_pckt vs_info ms_info spd_info audio_info avi_info cs_data_valid av_mute audio_ch_md audio_mode_change gen_ctl_pckt audio_c_pckt gamut_mdata hdmi_mode hdmi_encrpt new_isrc2_info new_isrc1_info new_acp_info new_vs_info new_ms_info new_spd_info new_audio_info new_avi_info fifo_near_ovfl...
Page 405 ADV7850 tri1_int_status[1:0], AFE, Address 0x1B[7:6] (Read Only) This readback displays the Tri1 interrupt status. Function tri1_int_status[1:0] Description 00  No signal change detected Signal crossed lower slice level Signal crossed upper slice level Signal crossed both slice levels tri2_int_status[1:0], AFE, Address 0x1B[5:4] (Read Only) This readback displays the Tri2 interrupt status.
Page 406 ADV7850 tri6_int_status[1:0], AFE, Address 0x1C[5:4] (Read Only) This readback displays the Tri6 interrupt status. Function tri6_int_status[1:0] Description 00  No signal change detected Signal crossed lower slice level Signal crossed upper slice level Signal crossed both slice levels tri7_int_status[1:0], AFE, Address 0x1C[3:2] (Read Only) This readback displays the Tri7 interrupt status.
Page 407 ADV7850 Function mv_ps_det_st Description 0  No Macrovision pseudo sync detection interrupt event occurred Macrovision pseudo sync detected interrupt event occurred stdi_data_valid_st, IO, Address 0x43[4] (Read Only) This readback indicates the latched signal status of the STDI valid interrupt signal. Once set, this bit remains high until the interrupt is cleared via stdi_data_valid_clr.
Page 408 ADV7850 Function mv_cs_det_st Description 0  Macrovision color stripe detected interrupt event not occurred Macrovision color stripe detected interrupt event occurred cp_cgms_chngd_st, IO, Address 0x48[2] (Read Only) This readback indicates the latched signal status of the CP CGMS changed interrupt signal. Once set, this bit remains high until the interrupt is cleared via cp_cgms_chngd_clr.
Page 409 ADV7850 Function vitc_avl_st Description 0  No VITC data available interrupt event occurred VITC data available interrupt event occurred gs_data_type_st, IO, Address 0x52[5] (Read Only) This readback indicates the latched status of the Gemstar type available interrupt signal. Once set, this bit remains high until the interrupt is cleared via gs_data_type_clr.
Page 410 ADV7850 Function ccap_avl_st Description 0  No closed captioning data available interrupt event occurred Closed captioning data available interrupt event occurred The interrupt_status_5 register consists of the following fields. sdp_progressive_st, Addr 40 (IO), Address 0x57[7] (Read Only) Function sdp_progressive_st Description 0 <<...
Page 411 ADV7850 Function stdi_dvalid_ch2_st Description 0  No STDI valid for sync channel 2 interrupt occurred STDI valid for sync channel 2 interrupt occurred cp_lock_ch1_st, IO, Address 0x5C[3] (Read Only) This readback indicates that STDI channel 1 has changed from an unlocked state to a locked state.
Page 412 ADV7850 Function isrc1_pckt_st Description 0  No interrupt generated isrc1_packet_raw changed, interrupt generated acp_pckt_st, IO, Address 0x61[5] (Read Only) This readback indicates the latched status of the audio content protection packet detected interrupt signal. Once set, this bit remains high until the interrupt is cleared via acp_info_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 mask bit.
Page 413 ADV7850 The HDMI Lvl INT Status 2 register consists of the following fields. cs_data_valid_st, IO, Address 0x66[7] (Read Only) This readback indicates the latched status of the channel status data valid interrupt signal. Once set, this bit remains high until the interrupt is cleared via cs_data_valid_clr.
Page 414 ADV7850 gen_ctl_pckt_st, IO, Address 0x66[2] (Read Only) This readback indicates the latched status of the general control packet interrupt signal. Once set, this bit remains high until the interrupt is cleared via gen_ctl_pckt_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Page 415 ADV7850 tmdspll_lck_c_st, IO, Address 0x6B[5] (Read Only) This readback indicates the latched status of the Port C TMDS PLL lock interrupt signal. Once set, this bit remains high until the interrupt is cleared via tmdspll_lck_c_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Page 416 ADV7850 Function tmds_clk_d_st Description 0  tmds_clk_d_raw not changed, interrupt not generated tmds_clk_d_raw changed, interrupt generated The HDMI Lvl INT Status 4 register consists of the following fields. hdmi_encrpt_a_st, IO, Address 0x70[7] (Read Only) This readback indicates the latched status of the Port A encryption detection interrupt signal. Once set, this bit remains high until the interrupt is cleared via hdmi_encrpt_a_clr.
Page 417 ADV7850 Function cable_det_a_st Description 0  cable_det_a_raw not changed, interrupt not generated cable_det_a_raw changed, interrupt generated . cable_det_b_st, IO, Address 0x70[2] (Read Only) This readback indicates the latched status for the Port B +5 V cable detection interrupt signal. Once set, this bit remains high until the interrupt is cleared via cable_det_b_clr.
Page 418 ADV7850 Function v_locked_st Description 0  v_locked_raw not changed, interrupt not generated v_locked_raw changed, interrupt generated de_regen_lck_st, IO, Address 0x75[0] (Read Only) This readback indicates the latched status of the DE regeneration lock interrupt signal. Once set, this bit remains high until the interrupt is cleared via de_regen_lck_clr.
Page 419 ADV7850 Function new_vs_info_st Description 0  No new VS packet received, interrupt not generated VS packet with new content received, interrupt generated new_ms_info_st, IO, Address 0x7A[3] (Read Only) This readback indicates the latched status for the New MPEG Source InfoFrame interrupt. Once set, this bit remains high until the interrupt is cleared via new_ms_info_clr.
Page 420 ADV7850 Function fifo_underflo_st Description 0  Audio FIFO not underflowed Audio FIFO underflowed fifo_overflo_st, IO, Address 0x7F[5] (Read Only) This readback indicates the latched status for the audio FIFO overflow interrupt. Once set, this bit remains high until the interrupt is cleared via fifo_overflo_clr.
Page 421 ADV7850 new_gamut_mdata_st, IO, Address 0x7F[0] (Read Only) This readback indicates the latched status for the new gamut metadata packet interrupt. Once set, this bit remains high until the interrupt is cleared via new_gamut_mdata_pckt_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Page 422 ADV7850 new_samp_rt_st, IO, Address 0x84[3] (Read Only) This readback indicates the latched status of the new sample rate interrupt. Once set, this bit remains high until the interrupt is cleared via new_samp_rt_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit...
Page 423 ADV7850 spd_inf_cks_err_st, IO, Address 0x89[6] (Read Only) This readback indicates the latched status of the SPD InfoFrame checksum error interrupt. Once set, this bit remains high until the interrupt is cleared via spd_inf_cks_err_clr. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Page 424 ADV7850 Function aksv_update_c_st Description 0  No AKSV updates on Port C Detected a write access to the AKSV register on Port C aksv_update_d_st, IO, Address 0x89[0] (Read Only) This readback indicates the latched status of Port D AKSV update interrupt. Once set, this bit remains high until the interrupt is cleared via aksv_update_d_clr.
Page 425: Processing Analog Front End Interrupts
These interrupts are located in AFE Map, addresses 0x1B and 0x1C. Each interrupt signal has a separate mask and clear signal available to the user. These are located in the AFE Map, addresses 0x17 to 0x1A. Refer to the ADV7850 Software Manual, AFE Map section, for more details.
Page 426: Tx Core
Figure 148: Processing Trilevel Interrupts 15.6 TX CORE This section describes the interrupt support provided for the Tx core of the ADV7850.The Tx interrupts are available on INT1 pin only. Interrupt Architecture Overview 15.6.1 This section describes the available HDMI Tx interrupts: •...
Page 427: Interrupt Bits
ADV7850 15.6.1.1 Interrupt Bits Interrupt bits are used to notify if a specific event has occurred or is active. When an interrupt bit become active, it is set to 1 until the user clears it by setting it to 0. The Tx interrupt bits are described here.
Page 428: Interrupt Mask Bits
ADV7850 15.6.1.2 Interrupt Mask Bits The interrupts mask bits are used to selectively activate an interrupt bit on the interrupt out pin INT0. The interrupt output pin is active when one or more interrupts bits are set and their corresponding interrupt mask bit is also set. Note that any given mask bit does not affect its corresponding interrupt bit but only affects the level on the interrupt output pin INT0.
Page 429: Pcb Layout Recommendations
PCB LAYOUT RECOMMENDATIONS The ADV7850 is a high precision, high speed, mixed signal device. It is important to have a well designed PCB board in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV7850.
Page 430: Power Supply Sequencing
Note: In this case, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level, as the supplies are being established. 16.3.1.2 Power Down Sequence The ADV7850 supplies may be de-asserted simultaneously as long as a higher rated supply does not go below a lower rated supply. Rev. A May 2012...
Page 431: Digital Outputs (Data And Clocks)
Adding a series resistor of a value between 50 to 200 ohms can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7850. If series resistors are used, they should be placed as close as possible to the ADV7850 pins and the trace impedance for these signals should match that of the termination resistors selected.
Page 432 C is usually 2 to 3 pF, depending on board traces and C (pin-to-ground-capacitance) is 4 pF for the ADV7850. stray Example: = 30 pF, C1 = 50 pF, C2 = 50 pF (in this case, 47 pF is the nearest real-life cap value to 50 pF) load Rev.
Page 433: Adv7850 Typical Connection Diagrams
ADV7850 17 APPENDIX B 17.1 ADV7850 TYPICAL CONNECTION DIAGRAMS Figure 152: ADV7850 Analog Input Connections (1) Rev. A May 2012...
Page 434: Figure 153: Adv7850 Analog Input Connections (2)
ADV7850 Figure 153: ADV7850 Analog Input Connections (2) Rev. A May 2012...
Page 435: Figure 154: Adv7850 Hdmi Input Connections (1)
ADV7850 Figure 154: ADV7850 HDMI Input Connections (1) Rev. A May 2012...
Page 436: Figure 155: Adv7850 Hdmi Input Connections (2)
ADV7850 Figure 155: ADV7850 HDMI Input Connections (2) Figure 156: ADV7850 HDMI Output Connections Rev. A May 2012...
Page 437: Figure 157: Adv7850 Audio Connections
ADV7850 Figure 157: ADV7850 Audio Connections Figure 158: ADV7850 Crystal and SPI EEPROM Connections Rev. A May 2012...
Page 438: Figure 159: Adv7850 Ddr2 Memory Connections
ADV7850 Figure 159: ADV7850 DDR2 Memory Connections Rev. A May 2012...
Page 439: Figure 160: Adv7850 Power Supply Connections
ADV7850 Figure 160: ADV7850 Power Supply Connections Rev. A May 2012...
Page 440: Package Outline Drawing
HDCP keys. An ATV motherboard is also required to process the ADV7850 digital outputs and achieve video output. An ATV video output board is optional to evaluate performance through an HDMI transmitter and video encoder.
Page 441: Recommended Unused Pin Configurations
ADV7850 19 APPENDIX D 19.1 RECOMMENDED UNUSED PIN CONFIGURATIONS Table 108: Recommended Configuration of Unused Pins Location Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground Ground Ground RXB_2+ HDMI Input Float this pin RXB_1+ HDMI Input Float this pin...
Page 442 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground Ground Ground Ground Ground VDD_EEPROM Power This pin must be decoupled to GND with a 100nF capacitor. TVDD Power This pin is always connected to Terminator supply voltage (3.3 V)
Page 443 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used RXB_5V HDMI Input This pin should be tied to 5 V PLL_LF Miscellaneous Analog This pin is always connected to the external PLL loop filter circuit Ground Ground ACMUXIN_4R Analog Audio Input...
Page 444 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground AC_AVDD Power This pin is always connected to the Audio block supply (3.3V) Ground Ground ISET Miscellaneous analog...
Page 445 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used Miscellaneous digital This pin is always connected to the I2C clock line of a control processor Power This pin is always connected to Digital core supply voltage (1.8 V) Ground Ground...
Page 446 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground Ground Ground TTX_SCLK Miscellaneous digital Float this pin TTX_MOSI Miscellaneous digital Float this pin TTX_MISO Miscellaneous digital Float this pin TTX_CSB Miscellaneous digital Float this pin Power This pin is always connected to Digital core supply voltage (1.8 V)
Page 447 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used Ground Ground Ground Ground Ground Ground AVIN13 Analog Video Input Float this pin AVIN12 Analog Video Input Float this pin AVIN11 Analog Video Input Float this pin AVIN10 Analog Video Input...
Page 448 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used AA10 Ground Ground AA11 SDRAM Interface Tie to ground via a 4k7 resistor AA12 SDRAM Interface Tie to ground via a 4k7 resistor AA13 SDRAM Interface Tie to ground via a 4k7 resistor...
Page 449 ADV7850 Location Mnemonic Type Recommended Configuration if Not Used AC18 AVIN1 Analog Video Input Float this pin AC19 AVIN2 Analog Video Input Float this pin AC20 Ground Ground AC21 AVIN4 Analog Video Input Float this pin AC22 AVIN5 Analog Video Input...
Page 450: List Of Figures
Figure 7: Video Input Signal Level After Voltage Clamps ..........................43 Figure 8: SDP Clamping Overview ................................... 44 Figure 9: ADV7850 Typical Configurations ..............................45 Figure 10: ADV7850 Input Functional Diagram ............................46 Figure 11: Synchronization Stripper Circuit ..............................51 Figure 12: D-Terminal Resistor Dividers ................................. 54 Figure 13: Trilevel Slicer .....................................
Page 451 Figure 60: Vertical Parameters for Field 1 ..............................176 Figure 61: Audio Processor Block Diagram ..............................178 Figure 62: Audio FIFO ...................................... 179 Figure 63: Monitoring Audio Packet Type Processed by ADV7850 ......................183 Figure 64: Timing Audio Data Output in I S Mode ............................. 186 Figure 65: Timing Audio Data Output in Right Justified Mode .........................
Page 452 Figure 125: IEC60958 Sub Stream ................................... 367 Figure 126: AES3 Stream Format Input to ADV7850 ..........................367 Figure 127: Timing of Standard I2S Stream Input to ADV7850 ........................ 367 Figure 128: Timing for Right-Justified I2S Stream Input to ADV7850 ..................... 368 Figure 129: Timing for Left-Justified I2S Stream Input to ADV7850 ......................
Page 453 Figure 156: ADV7850 HDMI Output Connections ............................. 436 Figure 157: ADV7850 Audio Connections ..............................437 Figure 158: ADV7850 Crystal and SPI EEPROM Connections ......................... 437 Figure 159: ADV7850 DDR2 Memory Connections ........................... 438 Figure 160: ADV7850 Power Supply Connections ............................439 Figure 161 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-425-1) Dimensions shown in millimeters ....
Page 454: List Of Tables
ADV7850 LIST OF TABLES Table 1: Function Descriptions ..................................20 Table 2: Primary Mode and Video Standard Selection ..........................36 Table 3: Vertical Frequencies Supported in HD Modes ..........................40 Table 4: Manual Input Muxing ..................................48 Table 5: Recommended Video Signal to ADC Routing ..........................49 Table 6: Available Inputs on Aout1 and Aout2 ...............................
Page 455 Table 97: Recommended N and Expected CTS Values for 48 kHz and Multiples .................. 373 Table 98: I S Channel Status ADV7850 Register Map Location of Fixed Value ..................375 Table 99: Audio InfoFrame Configuration Registers ........................... 378 Table 100: ACP Packet Configuration Registers ............................378 Table 101: ISRC1 Packet Configuration Registers ............................
Page 456 ADV7850 Table 103: KSV Fields Accessed From EDID Map ............................384 Table 104: Register Maps and I C Addresses ..............................388 Table 105: HDMI Interrupts Group 1 ................................403 Table 106: HDMI Interrupts Group 2 ................................403 Table 107: HDMI Interrupts Group 3 ................................404 Table 108: Recommended Configuration of Unused Pins ..........................
Page 457: List Of Equations
ADV7850 LIST OF EQUATIONS Equation 1: SDP Luma Gain Formula ................................83 Equation 2: SDP Chroma Gain Formula ................................. 84 Equation 3: TMDS Frequency in MHz (Measured After TMDS PLL) ...................... 155 Equation 4: Unit Time of Horizontal Filter Measurements ........................169 Equation 5: Relationship Between MCLKOUT, MCLKFS_N, and f ......................
Page 458: Revision History
ADV7850 REVISION HISTORY February 2012 Rev. 0 Initial version May 2012 Rev.A Removed Confidential from the document Updated CP FreeRun controls Removed Section 13.15 Rev. A May 2012...