Synchronization Slicers; Synchronization Filter Stage - Analog Devices ADV7850 Hardware Manual

Function
emb_sync_1_sel_man[1
:0]
00 
01
10
11
emb_sync_2_sel_man[1:0], AFE, Address 0x15[5:4]
This control is used to select a manual embedded synchronization for emb_sync2.
Function
emb_sync_2_sel_man[1
:0]
00 
01
10
11

5.8 SYNCHRONIZATION SLICERS

The ADV7850 has two synchronization slicer blocks, which are placed before the synchronization processing sections, as shown in
Figure 10. The purpose of a synchronization slicer is to provide a reliable synchronization signal to the STDI and SSPD circuits in the
component processor so that a robust identification of standard is made. A second synchronization slicer is provided to allow processing
of a second or, possibly, a third channel.
A more in depth picture of Sync Slicer 1 is shown in

Synchronization Filter Stage

5.8.1
There are two synchronization strippers in the ADV7850 similar to that shown in
2, and SYNC 3 can be routed to the filter stage.
sync1_filter_sel[1:0], AFE, Address 0x15[3:2]
This control is used to select the clamp filter on sync channel 1.
Function
sync1_filter_sel[1:0]
00
01
10 
11
sync2_filter_sel[1:0], AFE, Address 0x15[1:0]
This control is used to select the clamp filter on sync channel 2.
Function
sync2_filter_sel[1:0]
00
01
10 
11
Rev. A May 2012
Description
Sync1 pin
Sync2 pin
Sync3 pin
Reserved
Description
Sync1 pin
Sync2 pin
Sync3 pin
Reserved
Figure 11. The circuit is duplicated for Sync Slicer 2.
Description
No filter
Sync > 250 ns
Sync > 1 us
Sync > 2.5 us
Description
No filter
Sync > 250 ns
Sync > 1 us
Sync > 2.5 us
Figure 11. Any of the three SYNC pins; SYNC 1, SYNC
52
ADV7850