Pcb Layout Recommendations; Analogue Interface Inputs; Power Supply Bypassing; Figure 149: Recommended Power Supply Decoupling - Analog Devices ADV7850 Hardware Manual

16 APPENDIX A

16.1

PCB LAYOUT RECOMMENDATIONS

The ADV7850 is a high precision, high speed, mixed signal device. It is important to have a well designed PCB board in order to achieve
the maximum performance from the part. The following sections are a guide for designing a board using the ADV7850.
16.2

ANALOGUE INTERFACE INPUTS

The trace length running into the graphics inputs should be minimized. This is accomplished by placing the ADV7850 as close as possible
to the graphic connector. Long input trace lengths are undesirable because they pick up noise from the board and other external sources.
The voltage divider 24 ohm/51 ohm, which acts as a 75 ohm termination (refer to Appendix 17), should be placed as close as possible to
the ADV7850 chip. Any additional trace length between the termination resistors and the input of the ADV7850 increases the magnitude
of reflections, which corrupts the graphics signal. 75 ohm matched impedance traces should be used. Trace impedances other than 75
ohms also increase the chance of reflections.
The ADV7850 has high input bandwidth. While this is desirable for acquiring a high resolution PC graphics signal with fast edges, it
means that it also captures high frequency noise that is present. Therefore, it is important to reduce the amount of noise that is coupled to
the inputs. The designer should avoid running any digital traces near the analog inputs and ensure signal traces do not run too close
together to avoid crosstalk.
The non graphics input should also receive care when being routed on the PCB. Again, track lengths should be kept to a minimum and 75
ohm traces impedances should be used where possible.
The following routing is strongly recommended:
• RGB Graphics − Ain 1, 2, 3
• Component − Ain 4, 5, 6
• SCART (RGB) − Ain 7, 8, 9 (CVBS-Ain10)
• CVBS – Ain11
16.3

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor where possible. The fundamental idea is to have a
bypass capacitor within about 0.5 cm of each power pin.
The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power
plane to the capacitor to the power pin. The power connection should not be made between the capacitor and the power pin. Generally,
the best approach is to place a via underneath the 100 nF capacitor pads down to the power plane (refer to
It is particularly important to maintain low noise and good stability of the PVDD (the clock generator supply). Abrupt changes in the
PVDD supply can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to provide separately regulated and heavily filtered supplies for each of the analog
circuitry groups (AVDD, CVDD, TVDD, and PVDD).
Rev. A May 2012
via to GND layer
and GND pin
10nF
via to VDD pin

Figure 149: Recommended Power Supply Decoupling

429
0.1uF
VDD supply
ADV7850
Figure 149).